JPS62185348A - Bonding method for chip part - Google Patents

Bonding method for chip part

Info

Publication number
JPS62185348A
JPS62185348A JP61026818A JP2681886A JPS62185348A JP S62185348 A JPS62185348 A JP S62185348A JP 61026818 A JP61026818 A JP 61026818A JP 2681886 A JP2681886 A JP 2681886A JP S62185348 A JPS62185348 A JP S62185348A
Authority
JP
Japan
Prior art keywords
substrate
chip component
adhesives
chip
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61026818A
Other languages
Japanese (ja)
Inventor
Masahiro Yoshida
昌弘 吉田
Saburo Iida
飯田　三郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP61026818A priority Critical patent/JPS62185348A/en
Publication of JPS62185348A publication Critical patent/JPS62185348A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To connect a chip part precisely onto a substrate by forming a recessed section to the back of the chip part, previously flowing adhesives into the recessed section and bonding the chip part with the substrate. CONSTITUTION:A chip part 3, to the back thereof a recessed section 6 is shaped, is prepared. Adhesives 5 are flowed into the recessed section 6. The part 3 is turned over, and aligned with the predetermined position of a substrate 1. The part 3 is placed on the substrate 1. Consequently, adhesives 5 begin to flow out, and the part 3 is bonded onto the substrate 1. Excess adhesives are left in the recessed section 6 when adhesives 5 are surplus, and the whole adhesives 5 begin to flow out so as to contribute to bonding when adhesives 5 are little. Leads 4 for the part 3 are soldered. Accordingly, the chip part can be bonded with the substrate properly without being affected by the quantity of adhesives 5.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、チップ部品の基板への接着方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for bonding a chip component to a substrate.

（従来の技術） 従来、チップ部品は、第４図に示されるように、その裏
面は、略平坦な形状をしている。そして、両面実装等を
行う場合には基板の裏面のチップ部品が落下しないよう
に、ディスペンサ等を使用し、接着剤で基板にチップ部
品を固定してから、半田デイツプ槽等で半田付けを行な
うようにしている。(Prior Art) Conventionally, as shown in FIG. 4, the back surface of a chip component has a substantially flat shape. When performing double-sided mounting, etc., use a dispenser etc. to fix the chip components to the board with adhesive to prevent the chip components on the back side of the board from falling off, and then solder them in a solder dip bath, etc. That's what I do.

（発明が解決しようとする問題点） しかしながら、上記のチップ部品の接着剤の量が過多の
場合には、第５図に示されるように、基板１の面からチ
ップ部品３が浮いて、半田付けを行う際、基板１上のチ
ップ部品用半田付はパッド部２とチップ部品３のリード
４とが十分に接触できないために、半田付けが十分に行
われない。つまり、チップ部品の半田付は部の信頼性が
低下する欠点があった。この欠点をな（すために、接着
剤を過少にすると、チップ部品の接着強度が弱く、部品
が落下するといった問題があった。(Problem to be Solved by the Invention) However, if the amount of adhesive on the chip component is excessive, as shown in FIG. When soldering the chip component on the board 1, the pad portion 2 and the lead 4 of the chip component 3 cannot be brought into sufficient contact with each other, so that the soldering is not performed satisfactorily. In other words, soldering of chip components has the disadvantage that the reliability of the parts decreases. In order to overcome this drawback, if the amount of adhesive is too small, the adhesive strength of the chip components will be weak and the components will fall.

本発明は、上記問題点を除去し、接着剤の量の変化によ
るチップ部品の接着強度の低減を防止し、チップ部品の
半田付けの信頼性を高め得るチップ部品の接着方法を提
供することを目的とする。The present invention aims to provide a method for bonding chip components that can eliminate the above-mentioned problems, prevent the adhesive strength of chip components from decreasing due to changes in the amount of adhesive, and improve the reliability of soldering chip components. purpose.

（問題点を解決するための手段） 本発明は、上記問題点を解決するために、チソプ部品の
接着方法において、チップ部品の裏面には凹部を設け、
このチップ部品を用いて、その裏面の凹部に予め、接着
剤を流し込み、チップ部品を基板に接着するようにした
ものである。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a method for adhering Chisop components by providing a recess on the back surface of the chip component,
Using this chip component, an adhesive is poured in advance into the recess on the back surface of the chip component to adhere the chip component to the substrate.

（作用） 本発明によれば、チップ部品の裏面には凹部を設け、こ
のチップ部品を用いて、その裏面の凹部に予め、接着剤
を流し込み、チップ部品を基板に接着するようにしたの
で、接着剤の量の過多、過、少を裏面の凹部で調整する
ことができ、接着剤の量に左右されず、最適な接着を行
うことができる。(Function) According to the present invention, a recess is provided on the back surface of the chip component, and adhesive is poured into the recess on the back surface of the chip component in advance to bond the chip component to the substrate. The amount of adhesive can be adjusted to be too much, too little, or too little using the recessed part on the back surface, and optimal adhesion can be achieved regardless of the amount of adhesive.

その結果、チップ部品のリードは基板上のチップ部品用
半田付はパッドに十分に接触することになり、チップ部
品の基板上への接続を的確に行うことができる。As a result, the leads of the chip components come into sufficient contact with the soldering pads for the chip components on the substrate, and the chip components can be accurately connected to the substrate.

（実施例） 以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第１図は本発明に係るチップ部品の接着工程図、第２図
は本発明のチップ部品の一実施例を示す裏面斜視図、第
３図は第２図のＩ［ｌ−１１１線断面図である。FIG. 1 is a diagram of the adhesion process of a chip component according to the present invention, FIG. 2 is a rear perspective view showing an embodiment of the chip component of the present invention, and FIG. 3 is a sectional view taken along the line I[l-111 in FIG. It is.

まず、本発明のチップ部品について説明する。First, the chip component of the present invention will be explained.

従来のチップ部品は、第４図に示されるように、チップ
部品の裏面は平坦であるが、本発明の千ノブ部品は、第
２図及び第３図に示されるように、チップ部品の裏面の
略中央部に凹部６を設ける。The back surface of the conventional chip component is flat as shown in FIG. 4, but the thousand knob component of the present invention has a flat back surface as shown in FIGS. 2 and 3. A recessed portion 6 is provided approximately in the center of.

この凹部６にはチップ部品を基板へ接着する接着剤が注
入される。An adhesive for bonding the chip component to the substrate is injected into the recess 6.

次に、本発明のチップ部品の接着方法を第１図を用いて
詳細に説明する。Next, the method for bonding chip components according to the present invention will be explained in detail with reference to FIG.

（１）まず、第１図（ａ）に示されるように、前記した
裏面に凹部６を設けたチップ部品３を用意する。(1) First, as shown in FIG. 1(a), the chip component 3 having the recess 6 provided on its back surface is prepared.

（２）次に、第１図（ｂ）に示されるように、そのチッ
プ部品３の凹部６に接着剤５を流し込む。(2) Next, as shown in FIG. 1(b), adhesive 5 is poured into the recess 6 of the chip component 3.

（３）次に、第１図（ｃ）に示されるように、そのチッ
プ部品３を裏返しにして基板１の所定位置に合わせる。(3) Next, as shown in FIG. 1(c), the chip component 3 is turned over and placed in a predetermined position on the substrate 1.

つまり、基板１上のチップ部品用半田付はパッド部２に
チップ部品３のリード４が一致するように位置決めを行
う。In other words, when soldering a chip component on the substrate 1, positioning is performed so that the lead 4 of the chip component 3 is aligned with the pad portion 2.

（４）次に、そのチップ部品３を基板１上に載置する。(4) Next, the chip component 3 is placed on the substrate 1.

すると、第１図（ｄ）に示されるように、接着剤５が流
れ出し、チップ部品３は基板１上に接着される。この場
合、接着剤５は凹部６から適量流れ出すことになる。つ
まり、接着剤５が過多の場合は余分の接着剤は凹部６に
残され、接着剤５が少ない場合は全ての接着剤５が接着
に寄与するように流れ出すことになる。Then, as shown in FIG. 1(d), the adhesive 5 flows out and the chip component 3 is bonded onto the substrate 1. In this case, an appropriate amount of the adhesive 5 will flow out from the recess 6. That is, if there is too much adhesive 5, the excess adhesive will remain in the recess 6, and if there is not enough adhesive 5, all the adhesive 5 will flow out to contribute to adhesion.

更に、その後、この基板ｌを半田デイツプ槽に浸してチ
ップ部品３のリード４の半田付けを行うことにより、チ
ップ部品３が実装されたハイブリッドＩＣが得られる。Furthermore, after that, this substrate 1 is immersed in a solder dip tank and the leads 4 of the chip components 3 are soldered, thereby obtaining a hybrid IC on which the chip components 3 are mounted.

なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

（発明の効果） 以上、詳細に説明したように、本発明によれば、面実装
を行うチップ部品の接着方法において、裏面に接着剤の
注入が可能な凹部を有するチップ部品を用意し、該チッ
プ部品の凹部に接着剤を注入し、次に、該チッーブ部品
を裏返して基板に載置し、該チップ部品を基板へ接着す
るようにしたので、接着剤の量に影響されることなく、
チップ部品の基板への接着を適切に行うことができ、信
頼性の高いチップ部品の基板への接着及び半田付けを行
うことができる。また、接着剤を使用しない場合は、通
常のチップ部品と同様な使用が可能である。(Effects of the Invention) As described in detail above, according to the present invention, in the bonding method for surface-mounted chip components, a chip component having a recess into which an adhesive can be injected on the back surface is prepared, Adhesive is injected into the recess of the chip component, then the chip component is turned over and placed on the board, and the chip component is bonded to the board, without being affected by the amount of adhesive.
The chip components can be properly bonded to the substrate, and the chip components can be bonded and soldered to the substrate with high reliability. Furthermore, if no adhesive is used, it can be used in the same way as a normal chip component.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係るチップ部品の接着工程図、第２図
は本発明のチップ部品の裏面斜視図、第３図は第２図の
■−■線断面図、第４図は従来のチップ部品の裏面斜視
図、第５図は従来のチップ部品の接着説明図である。 １・・・基板、２・・・半田付はパッド部、３・・・チ
ップ部品、４・・・リード、５・・・接着剤、６・・・
凹部。Figure 1 is a diagram of the bonding process of a chip component according to the present invention, Figure 2 is a rear perspective view of the chip component of the present invention, Figure 3 is a sectional view taken along the line ■-■ in Figure 2, and Figure 4 is a conventional bonding process diagram. FIG. 5, which is a perspective view of the back side of the chip component, is an explanatory diagram of conventional bonding of the chip component. 1... Board, 2... Pad part for soldering, 3... Chip components, 4... Lead, 5... Adhesive, 6...
recess.

Claims (1)

【特許請求の範囲】[Claims] 面実装を行うチップ部品の接着方法において、裏面に接
着剤の注入が可能な凹部を有するチップ部品を用意する
工程と、該チップ部品の凹部に接着剤を注入する工程と
、該チップ部品を裏返して基板に載置する工程と、該チ
ップ部品を基板へ接着する工程とを順に施すようにした
ことを特徴とするチップ部品の接着方法。A method for bonding chip components for surface mounting includes a step of preparing a chip component having a recess on the back surface into which an adhesive can be injected, a step of injecting adhesive into the recess of the chip component, and a step of turning the chip component over. 1. A method for adhering a chip component, characterized in that a step of placing the chip component on a substrate and a step of bonding the chip component to the substrate are carried out in sequence.
JP61026818A 1986-02-12 1986-02-12 Bonding method for chip part Pending JPS62185348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61026818A JPS62185348A (en) 1986-02-12 1986-02-12 Bonding method for chip part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61026818A JPS62185348A (en) 1986-02-12 1986-02-12 Bonding method for chip part

Publications (1)

Publication Number Publication Date
JPS62185348A true JPS62185348A (en) 1987-08-13

Family

ID=12203856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61026818A Pending JPS62185348A (en) 1986-02-12 1986-02-12 Bonding method for chip part

Country Status (1)

Country Link
JP (1) JPS62185348A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5314842A (en) * 1988-09-30 1994-05-24 Kabushiki Kaisha Toshiba Resin-sealed type semiconductor device and method for manufacturing the same
WO2003061006A3 (en) * 2002-01-09 2004-06-17 Micron Technology Inc Stacked die in die bga package

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5314842A (en) * 1988-09-30 1994-05-24 Kabushiki Kaisha Toshiba Resin-sealed type semiconductor device and method for manufacturing the same
WO2003061006A3 (en) * 2002-01-09 2004-06-17 Micron Technology Inc Stacked die in die bga package
US7282392B2 (en) 2002-01-09 2007-10-16 Micron Technology, Inc. Method of fabricating a stacked die in die BGA package
US7282390B2 (en) 2002-01-09 2007-10-16 Micron Technology, Inc. Stacked die-in-die BGA package with die having a recess
US7309623B2 (en) 2002-01-09 2007-12-18 Micron Technology, Inc. Method of fabricating a stacked die in die BGA package
US7332819B2 (en) 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US7332820B2 (en) 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US7344969B2 (en) 2002-01-09 2008-03-18 Micron Technology, Inc. Stacked die in die BGA package
US7358117B2 (en) 2002-01-09 2008-04-15 Micron Technology, Inc. Stacked die in die BGA package
US7371608B2 (en) 2002-01-09 2008-05-13 Micron Technology, Inc. Method of fabricating a stacked die having a recess in a die BGA package
US20080136045A1 (en) * 2002-01-09 2008-06-12 Micron Technology, Inc. Stacked die in die BGA package
US7575953B2 (en) 2002-01-09 2009-08-18 Micron Technology, Inc. Stacked die with a recess in a die BGA package
US7799610B2 (en) 2002-01-09 2010-09-21 Micron Technology, Inc. Method of fabricating a stacked die having a recess in a die BGA package
US8373277B2 (en) * 2002-01-09 2013-02-12 Micron Technology, Inc. Stacked die in die BGA package
US20130154117A1 (en) * 2002-01-09 2013-06-20 Micron Technology, Inc. Stacked die in die bga package

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