JPS6155932A - Leaded chip carrier - Google Patents

Leaded chip carrier

Info

Publication number
JPS6155932A
JPS6155932A JP17740184A JP17740184A JPS6155932A JP S6155932 A JPS6155932 A JP S6155932A JP 17740184 A JP17740184 A JP 17740184A JP 17740184 A JP17740184 A JP 17740184A JP S6155932 A JPS6155932 A JP S6155932A
Authority
JP
Japan
Prior art keywords
leads
groove
peripheral part
main body
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17740184A
Other languages
Japanese (ja)
Inventor
Kazunao Maru
丸　一直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17740184A priority Critical patent/JPS6155932A/en
Publication of JPS6155932A publication Critical patent/JPS6155932A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To effect a tentative fixing easily and firmly by providing the bottom plane of main body with a peripheral part, a groove inside said peripheral part which contains front ends of leads, and a pedestal part inside the groove which is a minute interval recess for the plane including the lowest level of the leads. CONSTITUTION:The bottom plane 1a of a main body 1 is provided with a peripheral part 11a, a groove 21a inside the part 11a, and a pedestal part 31a inside the groove 21. The leads 2 projecting from the side planes of a main body are bent and directed toward the bottom plane 1a along the side planes and the leads extend over the peripheral part 11a with being in close contact with the part 11a. The front ends of them are contained in the groove 21a. The pedestal part 31 is formed with comprising a recess of only minute interval (t) for the lowest level of the leads 2, i.e., the part where the leads 2 extend over the peripheral part 11 with being in close contact with it. The interval (t) attains the strong bond of a layer of adhesive agent 3 when the chip is fixed tentatively to a circuit board 104 with the adhesive agent layer 3 and is dipped in a solder fused liquid 105.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は集積回路のパッケージに関するもので、特に
サーフェイスマウント用に使用されるリーディドチップ
キャリヤの改良に関する。TECHNICAL FIELD OF THE INVENTION This invention relates to integrated circuit packaging, and more particularly to improved leaded chip carriers used for surface mounting.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来集積回路のパッケージングで、特にサーフェイスマ
ウントに使用されるリーディドチップキャリヤがある。Leading chip carriers are conventionally used in integrated circuit packaging, particularly for surface mounting.

このリーディドチップキャリヤ（Ｌｅａｄｅｄ　ｃｈｉ
ｐ　ｃａｒｒｉｅｒ以降ＬＣＣと略称する）は第３図に
示すように１例えばエポキシ樹脂のような電気絶縁材で
平板状に形成された本体（１０１）は底面（ｌｏｌａ）
がその額縁状の周辺部（ｌｌｌａ）と、その内側の凹部
（ｌｌｌｂ）に形成されている。そして、側面から突出
したリード（１０２，１０２・・・）は折曲げられ側面
に沿うように底面（１０１ａ）に向かい、底面の周辺部
（ｌｌｌａ）に密接してこれをまたぎ、内側の凹部（ｌ
ｌｌｂ）に先端部を収めている。This leaded chip carrier
As shown in FIG.
is formed in its frame-shaped peripheral portion (lla) and its inner recessed portion (llllb). Then, the leads (102, 102, . . . ) protruding from the side surfaces are bent to face the bottom surface (101a) along the side surfaces, closely straddle the peripheral portion (lla) of the bottom surface, and straddle the inner recess (101a). l
The tip is housed in llb).

次に上記ＬＣＣはサーフェイスマウントされるが、その
アセンブリ技術の代表的なものとしてはんだリフロー法
、はんだディップ法がある。まず、はんだリフロー法は
サーキットボートの所定のパターン上にはんだクリーム
を印刷し、これにＬＣＣをはじめ配設部品をマウントし
オーブン中を通過させてはんだクリーム中に含まれるは
んだ粒を溶融させ、上記部品をサーキットボードにはん
だ付けするものである６次のはんだディップ法は。Next, the above-mentioned LCC is surface mounted, and representative assembly techniques include solder reflow method and solder dip method. First, in the solder reflow method, solder cream is printed on a predetermined pattern of a circuit board, the LCC and other installed parts are mounted on this, and the solder cream is passed through an oven to melt the solder grains contained in the solder cream. The 6th order solder dip method is used to solder components to circuit boards.

サーキットボートの所定のパターン上に部品の底面とサ
ーキットボードとを接着剤等で仮留めしておき、サーキ
ットボードの部品取付面をはんだ槽中にディップするこ
とによりはんだづけするものである。The bottom surface of the component and the circuit board are temporarily fixed on a predetermined pattern of the circuit board with adhesive or the like, and the component mounting surface of the circuit board is soldered by dipping it into a solder bath.

上記アセンブリ技術に対し、従来のＬＣＣは第５図にも
示すように、底面の凹部（ｌｌｌｂ）がリードの最低位
を含む平面に対し２〜３霧鴎の間隔（Ｔ）がある、コノ
たメ、凹部（ｌｌｌｂ）ニ接着剤Ｎ（１０３）　ヲ塗り
サーキットボード（１０４）に仮留めしてはんだ融液（
１０５）にディップするとき、第６図に示すように接着
剤ＭＩ（１０３）は不安定な態様となり、良好な仮留め
が達成できない。In contrast to the above assembly technology, the conventional LCC has a concave part (lllb) on the bottom surface with a distance (T) of 2 to 3 degrees from the plane containing the lowest point of the lead, as shown in Fig. 5. 4. Apply adhesive N (103) to the recessed part (llllb).Temporarily fasten it to the circuit board (104) and apply the solder melt (
105), the adhesive MI (103) becomes unstable as shown in FIG. 6, and good temporary fixing cannot be achieved.

〔発明の目的〕[Purpose of the invention]

この発明ははんだディップ法によるサーフェイスマウン
トを達成できるようにＬＣＣの改良構造を提供する。The present invention provides an improved structure of LCC that allows surface mounting by solder dip method.

〔発明の概要〕[Summary of the invention]

この発明にかかるＬＣＣは、本体の側面がら突出したリ
ードを折曲し底面に沿わせたリーディドチップキャリヤ
において１本体の底面が、周辺部と、周辺部の内側でリ
ードの先端部を収める溝と、溝の内側の台部とを備え、
この台部はリードの最低位を含む平面に対して微小間隔
凹であることを特徴とするものである。The LCC according to the present invention is a lead chip carrier in which the leads protruding from the side surface of the main body are bent and placed along the bottom surface. and a base inside the groove,
This platform is characterized by being concave at a minute interval with respect to the plane containing the lowest point of the lead.

〔発明の実施例〕[Embodiments of the invention]

次にこの発明の１実施例を第１ないし第３図を参照して
詳細に説明する。なお、構造その他の説明において従来
と変わらない部分については図面に同じ符号を付けて示
し説明を省略する。Next, one embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3. In addition, in the structure and other explanations, parts that are the same as the conventional ones are indicated by the same reference numerals in the drawings, and the explanations are omitted.

図示の１実施例のＬＣＣにおける本体（１）は底面を除
き従来の本体（１０１）と同じ構成であるが。The main body (1) of the illustrated LCC in one embodiment has the same structure as the conventional main body (101) except for the bottom surface.

その底面（１ａ）は、周辺部（ｌｌａ）と、この周辺部
の内側の溝（２１ａ）と、この溝の内側に台部（３１ａ
）を備えてなり、本体の側面から突出したリード（２，
２・・・）は折曲げられ側面に沿うように底面（ｌａ）
に向かい。The bottom surface (1a) has a peripheral part (lla), a groove (21a) inside this peripheral part, and a platform part (31a) inside this groove.
) and a lead (2,
2...) is bent and the bottom (la) is folded along the side.
Head to.

底面の周辺部（ｌｌａ）に密接してこれをまたぎ、内側
の溝（２１ａ）に先端部を収めている。It closely straddles the peripheral part (lla) of the bottom surface, and the tip part is housed in the inner groove (21a).

次に、上記台部（３１ａ）はリードの最低位、すなわち
、リードが底面の周辺部（ｌｌａ）に密接してまたぐ部
分に対し、第２図に示すように微小間１４　（ｔ）だけ
凹に形成されている。この微小間隔（１，）は例えばｏ
、ｉ〜０　、３　ｍｍでよく、これにより第３図に示す
ように、サーキットボード（１０４）に接着剤層（３）
で仮留めしてはんだ融液（１０５）中にディップされる
際の接着剤層は強固な接着を達成する。Next, the base portion (31a) is recessed by a minute distance 14 (t) as shown in FIG. is formed. This minute interval (1,) is, for example, o
, i~0, 3 mm, which allows the adhesive layer (3) to be attached to the circuit board (104) as shown in FIG.
The adhesive layer achieves strong adhesion when temporarily attached and dipped into the solder melt (105).

〔発明の効果〕〔Effect of the invention〕

この発明によればＬＣＣをサーキットボードにはんだデ
ィップ法で取付する際の仮留が容易、かつ確実にできる
顕著な利点がある。また、はんだリフロー法によって取
付する際の取付位置のセルフアライメントにも全く支障
を生じない。According to the present invention, there is a remarkable advantage that temporary fixing can be easily and reliably performed when attaching an LCC to a circuit board by the solder dip method. Further, there is no problem in self-alignment of the mounting position when mounting by the solder reflow method.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の１実施例のＬＣＣに係り。 図（ａ）は上面の斜視図、図（ｂ）は底面の斜視図、第
２図はｌ実施例をさらに説明するための断面図、第３図
は１実施例のＬｃｃのはんだディップを説明するための
断面図、第４図は以降は従来のＬＣＣに係り、第４図（
ａ）は上面の斜視図１図（ｂ）は底面の斜視図、第５図
はＬＣＣをさらに説明するための断面図、第６図はＬＣ
Ｃのはんだディップを説明するための断面図である。 １　　　　　　ＬＣＣの本体 １８　　　　　本体の底面 １１ａ　　　　　底面の周辺部 ２１ａ　　　　　底面の溝 ３１ａ　　　　　底面の台部 ２　　　　　　リード ３　　　　　接着剤層FIG. 1 relates to an LCC according to one embodiment of the present invention. Figure (a) is a perspective view of the top, Figure (b) is a perspective view of the bottom, Figure 2 is a sectional view to further explain the l embodiment, and Figure 3 explains the solder dip of Lcc in the first embodiment. The sectional view shown in Fig. 4 is related to the conventional LCC, and Fig. 4 (
a) is a perspective view of the top surface; FIG. 5(b) is a perspective view of the bottom surface; FIG. 5 is a sectional view to further explain the LCC; and FIG.
FIG. 3 is a cross-sectional view for explaining the solder dip shown in FIG. 1 LCC main body 18 Bottom surface 11a of the main body Peripheral part 21a of the bottom surface Groove 31a of the bottom surface 2 Leads 3 Adhesive layer

Claims (1)

【特許請求の範囲】[Claims] 本体の側面から突出したリードを折曲し底面に沿わせた
リーディドチップキャリヤにおいて、本体の底面が、周
辺部と、周辺部の内側でリードの先端部を収める溝と、
溝の内側の台部を備え、この台部はリードの最低位を含
む平面に対して微小間隔凹であることを特徴とするリー
ディドチップキャリヤ。In a leaded chip carrier in which the leads protruding from the side surface of the main body are bent and placed along the bottom surface, the bottom surface of the main body has a peripheral part and a groove in which the tip of the lead is accommodated inside the peripheral part;
A leaded chip carrier comprising a pedestal inside the groove, the pedestal being concave at a minute distance with respect to a plane containing the lowest position of the leads.
JP17740184A 1984-08-28 1984-08-28 Leaded chip carrier Pending JPS6155932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17740184A JPS6155932A (en) 1984-08-28 1984-08-28 Leaded chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17740184A JPS6155932A (en) 1984-08-28 1984-08-28 Leaded chip carrier

Publications (1)

Publication Number Publication Date
JPS6155932A true JPS6155932A (en) 1986-03-20

Family

ID=16030281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17740184A Pending JPS6155932A (en) 1984-08-28 1984-08-28 Leaded chip carrier

Country Status (1)

Country Link
JP (1) JPS6155932A (en)

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