JPS59143353A - Manufacture of electronic component parts - Google Patents

Manufacture of electronic component parts

Info

Publication number
JPS59143353A
JPS59143353A JP1766183A JP1766183A JPS59143353A JP S59143353 A JPS59143353 A JP S59143353A JP 1766183 A JP1766183 A JP 1766183A JP 1766183 A JP1766183 A JP 1766183A JP S59143353 A JPS59143353 A JP S59143353A
Authority
JP
Japan
Prior art keywords
terminal
chip
hole
solder
terminal part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1766183A
Other languages
Japanese (ja)
Inventor
Toru Yamashita
徹 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1766183A priority Critical patent/JPS59143353A/en
Publication of JPS59143353A publication Critical patent/JPS59143353A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To facilitate positioning and thus increase the yield rate of product quality by a method wherein a through hole is bored in the terminal part, the terminal part of a chip is inserted thereinto, the chip is adhesion-fixed to the substrate, and the terminals parts thereof are connected with solder in the hole, when the LSI chip is bonded to the terminal part of the substrate composed of glass epoxy, paper phenol, etc. CONSTITUTION:As normal, a Cr layer 3, a CrCu layer 4, and a Cu layer 5 are formed by lamination on the Al terminal 2 of the LSI chip 1. Next, the terminal part 9 of the chip 1 formed in such a manner is inserted into the through hole 10 of the terminal 8 provided to the substrate 7 composed of glass epoxy, paper phenol, etc., and the substrate 7 and the chip 1 are first provisionally fixed at the middle of the hole 10 by means of an adhesive 11. Thereafter, it is dipped in a solder dipping bath, making solder 12 to flow into the hole 10, and thus the terminal part 9 is connected with solder to the terminal 8. Such a manner unnecessitates the process of solder plating to the terminal part 9 and then facilitates the positioning of the terminal part 9.

Description

【発明の詳細な説明】 く技術分野〉 本発明はガラスエポキシ、紙フェノール等からなる基板
の端子部にＬＳＩチップをボンディングして形成される
電子部品の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to the structure of an electronic component formed by bonding an LSI chip to a terminal portion of a substrate made of glass epoxy, paper phenol, or the like.

〈従来技術〉 従来の電子部品はマスク蒸着法により端子部にＣｒ層、
ＣｒＣｕ層およびＣｕ層を順に形成し、さらにその上に
半田メッキを施したＬＳＩチップをボンディング装置を
使用して基板に設けられた端子部にボンディングして構
成されている。<Prior art> Conventional electronic components have a Cr layer,
It is constructed by sequentially forming a CrCu layer and a Cu layer, and then bonding an LSI chip, which is solder-plated thereon, to a terminal portion provided on a substrate using a bonding device.

即ち、第１図乃至第３図に示す通り、まずＬＳＩチップ
ｌのＡｔ端子２にＣｒ層３、ＣｒＣｕ層４、Ｃｕ層５を
蒸着し、その上に半田メッキ層６を形成する。そして、
このように構成したＬＳＩチップ１の端子部６′ヲ基板
７の端子８に位置合せし、半田メッキ層６を溶かして前
記両端子部を接続している。That is, as shown in FIGS. 1 to 3, first, a Cr layer 3, a CrCu layer 4, and a Cu layer 5 are deposited on the At terminal 2 of the LSI chip 1, and a solder plating layer 6 is formed thereon. and,
The terminal portions 6' of the LSI chip 1 thus constructed are aligned with the terminals 8 of the substrate 7, and the solder plating layer 6 is melted to connect the two terminal portions.

しかしながら、このような接続構造によれば、半田メッ
キ層６の形成具合によってＬＳＩチップ端子の高さにバ
ラツキが生じ、ボンディング時に基板端子に全く接続さ
れないものとか接続不良のものが発生するという欠点が
あった。また、半田メッキの際の高熱がＬＳＩチップに
悪影響を与え、良品率の低下を招くという問題があり、
さらに半田メッキ部分が光学的に見えにくいので基板端
子部への位置合せが困難となり、作業能率が悪いという
欠点があった。However, this connection structure has the drawback that the height of the LSI chip terminals varies depending on the formation condition of the solder plating layer 6, and some terminals may not be connected to the board terminals at all or there may be poor connections during bonding. there were. In addition, there is the problem that the high heat during solder plating has a negative effect on LSI chips, leading to a decrease in the quality of products.
Furthermore, since the solder plated portion is optically difficult to see, it is difficult to align the solder plated portion to the terminal portion of the board, resulting in poor work efficiency.

〈目的〉 本発明はかかる従来の欠点に鑑みて成されたもので、Ｌ
ＳＩチップ端子への半田メッキ処理工程を省略して、ボ
ンディング時の良品率の向上並びに位置合せ作業能率の
向上が図れる新規な電子部の構造を提供せんとするもの
である。<Purpose> The present invention has been made in view of such conventional drawbacks, and
It is an object of the present invention to provide a new structure of an electronic part that can omit the solder plating process for SI chip terminals and improve the rate of non-defective products during bonding and the efficiency of alignment work.

〈実施例〉 以下図に基づいて本発明の詳細な説明する。<Example> The present invention will be described in detail below based on the figures.

第４図乃至第６図は本発明に係る電子部品の構造を説明
する図である。まず、ＬＳＩチップ１のＡｔ端子２には
従来通りマスク蒸着法によりＣｒ層３、ＣｒＣｕ層４及
びＣｕ層５が形成されており（第４図参照）、この様に
形成された端子部９は基板７の端子８に穿設されたスル
ーホール１０に挿入され、接着剤１１によって該ＬＳＩ
チップ１と基板７が仮固定される（第５図参照）。そし
て、仮固定されたＬＳＩチップ１と基板７は半田ディプ
装置のディピング槽に通され、これによりスルーホール
１０内に半田１２が流れ込み凝固して前（３） 記ＬＳＩチップの端子部９と基板端子８が半田接続され
ている。4 to 6 are diagrams for explaining the structure of the electronic component according to the present invention. First, a Cr layer 3, a CrCu layer 4, and a Cu layer 5 are formed on the At terminal 2 of the LSI chip 1 by conventional mask evaporation method (see FIG. 4), and the terminal portion 9 formed in this way is The LSI is inserted into a through hole 10 made in a terminal 8 of a board 7, and is attached with an adhesive 11.
The chip 1 and the substrate 7 are temporarily fixed (see FIG. 5). Then, the temporarily fixed LSI chip 1 and the board 7 are passed through a dipping tank of a solder dipping device, whereby the solder 12 flows into the through hole 10 and solidifies. Terminal 8 is connected by solder.

かかる電子部品の構造によれば、Ａｔ端子２にＣｒ　＋
　Ｃｒ　Ｃｕ、　Ｃｕ　　ｋ　マスク蒸着してなるＬＳ
Ｉチップｌの端子部９をそのまま基板端子のスルーホー
ル１０に挿入し、接着剤１１にてＬＳＩチップ１を基板
７に仮止めするとともに、これ全ディピング槽に通すこ
とによりスルーホール１０に流れ込んだ半田１２が凝固
してＬＳＩチップ端子部９と基板端子８を接続できるか
ら、前記チップ端子部９への半田メッキ処理が不要とな
る。このため、メッキ処理工程の省略と熱によるＬＳＩ
チップへの悪影響を防止することが出来るとともに、基
板端子８のスルーホール１１にＬＳＩチップ端子部９を
挿入するために位置合せが容易となる。According to the structure of such an electronic component, Cr +
LS made by Cr Cu, Cu k mask vapor deposition
The terminal part 9 of the I-chip 1 was inserted into the through-hole 10 of the board terminal as it was, and the LSI chip 1 was temporarily fixed to the board 7 with adhesive 11, and all of it flowed into the through-hole 10 by passing it through a dipping bath. Since the solder 12 solidifies and the LSI chip terminal portion 9 and the board terminal 8 can be connected, the solder plating process to the chip terminal portion 9 becomes unnecessary. For this reason, the plating process is omitted and LSI
Not only can an adverse effect on the chip be prevented, but also alignment is facilitated in order to insert the LSI chip terminal portion 9 into the through hole 11 of the board terminal 8.

〈効果〉 以上の様に本発明は、基板端子部にスルーホールを形成
し且つこのスルーホールにＬＳＩチップ前記ＬＳＩチッ
プ端子と前記基板端子を半田接続してなるから製造工程
中ＬＳＩチップ端子への半田メッキ処理工程全省略する
ことが出来、また凹凸関係によって端子間の位置合せが
容易に行える等良品率の向上並びに位置合せ作業の向上
を図ることが出来る。<Effects> As described above, in the present invention, a through hole is formed in the board terminal portion and the LSI chip terminal of the LSI chip and the board terminal are connected to the through hole by soldering. The entire solder plating process can be omitted, and the unevenness makes it possible to easily align the terminals, thereby improving the yield rate and alignment work.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図乃至第３図は従来の電子部品の構造及びその製造
工程を説明する図、第４図乃至第６図は本発明に係る電
子部品の構造及びその製造工程を説明する図である。 ｌはＬＳＩチップ、２はＡｔ端子、７は基板。 ８は端子、９はＬＳＩチップ端子部、１０はスル−ホー
ル、１１は接着剤、１２は半田 代理人　弁理士　福　士　愛　彦　（他２名）第１図 第２図 γ 第３図1 to 3 are diagrams for explaining the structure of a conventional electronic component and its manufacturing process, and FIGS. 4 to 6 are diagrams for explaining the structure of an electronic component and its manufacturing process according to the present invention. 1 is an LSI chip, 2 is an At terminal, and 7 is a board. 8 is a terminal, 9 is an LSI chip terminal part, 10 is a through hole, 11 is an adhesive, 12 is a solder agent, patent attorney Yoshihiko Fukushi (and 2 others), Figure 1, Figure 2, γ Figure 3

Claims (1)

【特許請求の範囲】 １　基板の端子部にＬＳＩチップをボンディングして形
成される電子部品に於て、 前記基板端子部にスルーホールを形成し、且つこのスル
ーホールに前記ＬＳＩチップの端子部を挿入し、該ＬＳ
Ｉチップと基板とを接着固定するとともに、前記スルー
ホール部において前記ＬＳＩチップ端子と前記基板端子
を半田接続してなることを特徴とする電子部品の構造。[Claims] 1. In an electronic component formed by bonding an LSI chip to a terminal portion of a substrate, a through hole is formed in the terminal portion of the substrate, and the terminal portion of the LSI chip is inserted into the through hole. Insert the LS
1. A structure of an electronic component, characterized in that an I-chip and a substrate are bonded and fixed, and the LSI chip terminal and the substrate terminal are connected by solder at the through-hole portion.
JP1766183A 1983-02-04 1983-02-04 Manufacture of electronic component parts Pending JPS59143353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1766183A JPS59143353A (en) 1983-02-04 1983-02-04 Manufacture of electronic component parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1766183A JPS59143353A (en) 1983-02-04 1983-02-04 Manufacture of electronic component parts

Publications (1)

Publication Number Publication Date
JPS59143353A true JPS59143353A (en) 1984-08-16

Family

ID=11950029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1766183A Pending JPS59143353A (en) 1983-02-04 1983-02-04 Manufacture of electronic component parts

Country Status (1)

Country Link
JP (1) JPS59143353A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2622741A1 (en) * 1987-11-04 1989-05-05 Nec Corp Structure for connecting substrates with different thermal expansion coefficients
JPH01198040A (en) * 1988-02-03 1989-08-09 Omron Tateisi Electron Co Mounting of semiconductor element
JPH03179756A (en) * 1990-11-02 1991-08-05 Seikosha Co Ltd Ic chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2622741A1 (en) * 1987-11-04 1989-05-05 Nec Corp Structure for connecting substrates with different thermal expansion coefficients
JPH01198040A (en) * 1988-02-03 1989-08-09 Omron Tateisi Electron Co Mounting of semiconductor element
JPH03179756A (en) * 1990-11-02 1991-08-05 Seikosha Co Ltd Ic chip

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