JPS5585957A - Logic circuit for test bit selection - Google Patents
Logic circuit for test bit selectionInfo
- Publication number
- JPS5585957A JPS5585957A JP14583078A JP14583078A JPS5585957A JP S5585957 A JPS5585957 A JP S5585957A JP 14583078 A JP14583078 A JP 14583078A JP 14583078 A JP14583078 A JP 14583078A JP S5585957 A JPS5585957 A JP S5585957A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- inputted
- output
- signal
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE: To enable one additional circuit independently of the number of test bits, by providing the detection circuit which is outputted with the higher level signal than H level address signal with the path of the address signal bit, and receiving the output with NOR gate.
CONSTITUTION: Among the two address signals A0, A1, the address signal A0 in common use with selection is inputted to the inverter I1 and level detection circuit LC, and the outputs are inputted to the 2-input NOR circuit NR0. The output of the circuit LC is 0 when the signal A0 is 0 and 1L and 1I when 1H only. The output of the inverter I1 and the gate NR0 is respectively fed to the NAND gates NG1, NG2. The output of the circuit LC is inputted to the NAND gates NG3, NG4 via the amplifier B0. The signal A1 is for selection of the test bits Tb1, Tb2 and inputted respectively to the gates NG3, NG4 via the inverters I3, I4. The word lines W1, W2 are selected in the combination of (00), (1L0) of A0, A1, and the test bit Tb1 is selected when A0 is 1H and A1 is 0, and Tb2when A0 is 1H and A1 is 1L.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53145830A JPS5853440B2 (en) | 1978-11-25 | 1978-11-25 | Logic circuit for test bit selection |
EP79302622A EP0011974B1 (en) | 1978-11-25 | 1979-11-19 | Programmable memory device provided with test means |
DE7979302622T DE2966682D1 (en) | 1978-11-25 | 1979-11-19 | Programmable memory device provided with test means |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53145830A JPS5853440B2 (en) | 1978-11-25 | 1978-11-25 | Logic circuit for test bit selection |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5585957A true JPS5585957A (en) | 1980-06-28 |
JPS5853440B2 JPS5853440B2 (en) | 1983-11-29 |
Family
ID=15394095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53145830A Expired JPS5853440B2 (en) | 1978-11-25 | 1978-11-25 | Logic circuit for test bit selection |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5853440B2 (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5755600A (en) * | 1980-08-14 | 1982-04-02 | Siemens Ag | Device for testing memory cell of semiconductor memory |
JPS5897800U (en) * | 1981-12-22 | 1983-07-02 | 日本電気株式会社 | memory device |
JPS58115828A (en) * | 1981-12-29 | 1983-07-09 | Fujitsu Ltd | Semiconductor integrated circuit |
JPS5960800A (en) * | 1982-08-30 | 1984-04-06 | シ−メンス・アクチエンゲゼルシヤフト | Digital semiconductor circuit |
JPS59217293A (en) * | 1983-05-25 | 1984-12-07 | Nec Corp | Semiconductor integrated circuit |
JPS6059599A (en) * | 1983-09-13 | 1985-04-05 | Nec Corp | Non-volatile semiconductor memory |
JPS60140600A (en) * | 1983-12-28 | 1985-07-25 | Oki Electric Ind Co Ltd | Nonvolatile memory device |
JPS6134800A (en) * | 1984-07-25 | 1986-02-19 | Nec Corp | Reading exclusive-use semiconductor memory device |
JPS62112300A (en) * | 1985-10-15 | 1987-05-23 | テキサス インスツルメンツ インコ−ポレイテツド | Array of programmable solid memory cell and testing therefor |
JPS62128099A (en) * | 1985-11-28 | 1987-06-10 | Fujitsu Ltd | Test circuit for one-time rom |
JPS6314400A (en) * | 1986-07-04 | 1988-01-21 | Toshiba Corp | Nonvolatile semiconductor memory |
-
1978
- 1978-11-25 JP JP53145830A patent/JPS5853440B2/en not_active Expired
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5755600A (en) * | 1980-08-14 | 1982-04-02 | Siemens Ag | Device for testing memory cell of semiconductor memory |
JPH0132600B2 (en) * | 1980-08-14 | 1989-07-06 | Siemens Ag | |
JPS6138160Y2 (en) * | 1981-12-22 | 1986-11-04 | ||
JPS5897800U (en) * | 1981-12-22 | 1983-07-02 | 日本電気株式会社 | memory device |
JPS58115828A (en) * | 1981-12-29 | 1983-07-09 | Fujitsu Ltd | Semiconductor integrated circuit |
JPH03719B2 (en) * | 1981-12-29 | 1991-01-08 | Fujitsu Ltd | |
JPS5960800A (en) * | 1982-08-30 | 1984-04-06 | シ−メンス・アクチエンゲゼルシヤフト | Digital semiconductor circuit |
JPH0524599B2 (en) * | 1982-08-30 | 1993-04-08 | Siemens Ag | |
JPS59217293A (en) * | 1983-05-25 | 1984-12-07 | Nec Corp | Semiconductor integrated circuit |
JPH0120520B2 (en) * | 1983-05-25 | 1989-04-17 | Nippon Electric Co | |
JPH0313680B2 (en) * | 1983-09-13 | 1991-02-25 | Nippon Electric Co | |
JPS6059599A (en) * | 1983-09-13 | 1985-04-05 | Nec Corp | Non-volatile semiconductor memory |
JPS60140600A (en) * | 1983-12-28 | 1985-07-25 | Oki Electric Ind Co Ltd | Nonvolatile memory device |
JPS6134800A (en) * | 1984-07-25 | 1986-02-19 | Nec Corp | Reading exclusive-use semiconductor memory device |
JPS62112300A (en) * | 1985-10-15 | 1987-05-23 | テキサス インスツルメンツ インコ−ポレイテツド | Array of programmable solid memory cell and testing therefor |
JPS62128099A (en) * | 1985-11-28 | 1987-06-10 | Fujitsu Ltd | Test circuit for one-time rom |
JPS6314400A (en) * | 1986-07-04 | 1988-01-21 | Toshiba Corp | Nonvolatile semiconductor memory |
Also Published As
Publication number | Publication date |
---|---|
JPS5853440B2 (en) | 1983-11-29 |
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