JPH0335496A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0335496A JPH0335496A JP1170263A JP17026389A JPH0335496A JP H0335496 A JPH0335496 A JP H0335496A JP 1170263 A JP1170263 A JP 1170263A JP 17026389 A JP17026389 A JP 17026389A JP H0335496 A JPH0335496 A JP H0335496A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- metal wire
- layer
- vcc
- parasitic resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 26
- 230000002093 peripheral effect Effects 0.000 claims abstract description 19
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 230000007257 malfunction Effects 0.000 abstract description 6
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は２層金属配線構成を持つ半導体装置における
金属配線の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a metal wiring structure in a semiconductor device having a two-layer metal wiring structure.
第２図は従来の２層金属配線構成を持つ半導体メモリ装
置のチップの平面図を示す０図においてｌはＩＣＣラン
プ体、２はメモリセルアレイ、及びデータを伝達する信
号配線、３は外部より電源ｖｃｃが供給されるＶ ｃｃ
バンドで、このｖｃｃバンド３よりＶ ｃｃ側周辺回路
７、ＧＮＤ側周辺回路８及び、メモリセルアレイ２に金
属配線を用いて電源ｖｃｃが供給される。ＧＮＤ側周辺
回路への電源Ｖ ｃｃの供給は長いＶ ｃｃ配ｖＡ５を
介して行なわれる。Fig. 2 shows a plan view of a chip of a semiconductor memory device having a conventional two-layer metal wiring structure. Vcc is supplied with Vcc
Power supply VCC is supplied from this VCC band 3 to the VCC side peripheral circuit 7, the GND side peripheral circuit 8, and the memory cell array 2 using metal wiring. Power supply Vcc is supplied to the GND side peripheral circuits via a long Vcc distribution VA5.
４は外部より接地電位ＧＮＤが供給されるＧＮＤパッド
で、このＧＮＤパッド４よりＶ ｃｃ側周辺回路７、Ｇ
ＮＤ側周辺回路８及びメモリセルアレイ２に金属配線を
用いて接地電位ＧＮＤが供給される。この時、Ｖ ｃｃ
側周辺回路への接地電位ＧＮＤの支給は長いＧＮＤ配ｗ
Ａ６を介して行なわれる。4 is a GND pad to which the ground potential GND is supplied from the outside, and peripheral circuits 7, G on the Vcc side from this GND pad 4
A ground potential GND is supplied to the ND side peripheral circuit 8 and the memory cell array 2 using metal wiring. At this time, Vcc
The supply of ground potential GND to the peripheral circuits on the side requires a long GND wiring.
This is done via A6.
通常、２層金属配線構成を持つｒｃチソブはＶ ｃｃ側
、ＧＮＤ側周辺回路７，８を１層目の金属配線、ｖｃｃ
ＳＧＮＤ配置％１５．６は２層目、メモリセルアレイ、
及びデータを伝達する信号配線は１層目、２層目の両層
の金属配線で構成されている。Normally, in an RC chip with a two-layer metal wiring configuration, the peripheral circuits 7 and 8 on the Vcc side and GND side are connected to the first layer of metal wiring, and
SGND placement %15.6 is the second layer, memory cell array,
The signal wiring for transmitting data is composed of metal wiring in both the first and second layers.
〔発明が解決しようとするＩＩ、り
しかしながら近年メモリ容量の増大に伴ない、チップサ
イズが増加してくるにつれて、上記のような長いＶ ｃ
ｃ配線及び長いＧＮＤ配線における金属配線の寄生抵抗
が無視できなくなって、ｖｃｃｃｃ側周辺回路いてＧＮ
Ｄが浮き上がったり、逆にＧＮＤ側周辺回路においてｖ
ｃｃにへたりが生じたりしてひいてはこれがノイズ不良
の原因になるという問題点が生じてきた。[The invention aims to solve II, However, in recent years, as the memory capacity has increased and the chip size has increased, the long V c
The parasitic resistance of the metal wiring in the c wiring and the long GND wiring can no longer be ignored, and the peripheral circuits on the vcccc side
If D rises, or conversely, V in the GND side peripheral circuit
A problem has arisen in that the cc becomes sagging, which in turn causes noise defects.
第３図は上記のノイズ不良が発生するメカニズムを示す
説明図で、図において、９，１０はＶ ｃｃ側周辺回路
７に含まれる反転回路である。第４図の波形（イ〉に示
した様に反転回路ｌＯに入力される信号ａが“Ｌ′から
“Ｈｏに変化すると、反転回路１０のＮｅｈｌ−ランジ
スタを通じて充放電電流ｉがＧＮＤに流れ込む、この時
、ＧＮＤパッド４の電位（ＯＮＤＩ）は第４図の波形（
ロ）に示す様に安定しているが、Ｖ−側周辺回路７の接
地電位（ＧＮＤ２）は長いＧＮＤ配線６の寄生抵抗Ｒの
為、充分速く電流を流し切れず、第４図の波形（ハ）に
示す様に一時的に浮き上がってしまう、その為、その他
の反転回路９に入力される信号すは、相対的に見れば、
第４図の波形（ニ）に示す様にノイズが入った様な状態
となる。このノイズが誤動作の原因となる。FIG. 3 is an explanatory diagram showing the mechanism by which the above noise defect occurs. In the figure, 9 and 10 are inverting circuits included in the Vcc side peripheral circuit 7. As shown in the waveform (a) of FIG. 4, when the signal a input to the inverting circuit 10 changes from "L' to "Ho, the charging/discharging current i flows into GND through the Nehl transistor of the inverting circuit 10. At this time, the potential (ONDI) of the GND pad 4 has the waveform (
Although the ground potential (GND2) of the V- side peripheral circuit 7 is stable as shown in Figure 4 (b), due to the parasitic resistance R of the long GND wiring 6, the current cannot flow through quickly enough, and the waveform shown in Figure 4 ( As shown in c), the signals that are input to the other inverting circuits 9 temporarily rise.
As shown in the waveform (d) of FIG. 4, a state appears in which noise appears. This noise causes malfunction.
この発明は上記の様な問題点を解消するためになされた
もので、寄生抵抗値を減少させることにより、ノイズに
よる誤動作の起こりにくい半導体装置を得ることを目的
とする。The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that is less likely to malfunction due to noise by reducing the parasitic resistance value.
〔課題を解決するための手段および作用〕この発明に係
る半導体装置は、２層金属配線部の２層目の金属配線を
、他の周辺回路、信号配線に使用せず、電源配線部のみ
に使用することにより、電源配線部の面積を増大させ、
その寄生抵抗（直を減少させたものである。[Means and effects for solving the problem] A semiconductor device according to the present invention does not use the second layer metal wiring of the two-layer metal wiring section for other peripheral circuits or signal wiring, but only for the power supply wiring section. By using this, the area of the power wiring section can be increased,
Its parasitic resistance (direction) is reduced.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例を示す半導体メモリ装置の
チップの平面図である０図に示す様に、２層目の金属配
線をメモリセルアレイ、信号配線２に使用していない為
、長いＶ ＣＣ配線５及び長いＧＮＤ配線６の金属配線
はその面積を多く配線できる。金属配線の寄生抵抗値Ｒ
はその面積に反比例するので、これにより電源配線の寄
生抵抗Ｒが減少すれば、第３図の例も第４図（ホ）に示
す様にｖｃｃｃｃ側周辺回路７地電位（ＧＮＤ２）の−
時的な浮き上がりも低減でき、反転回路９に入力する信
号（ｂ）にも、第４図（へ）に示す様にさほど大きなノ
イズとなって現われないので、誤動作に至る可能性は低
くなる。FIG. 1 is a plan view of a chip of a semiconductor memory device showing an embodiment of the present invention. As shown in FIG. The metal wiring of the VCC wiring 5 and the long GND wiring 6 can be wired over a large area. Parasitic resistance value R of metal wiring
is inversely proportional to its area, so if the parasitic resistance R of the power supply wiring is reduced, the example of FIG.
Temporal fluctuations can also be reduced, and the signal (b) input to the inverting circuit 9 does not appear as a very large noise as shown in FIG.
以上のように、この発明によれば、２層金属配線構成を
持つ半導体装置の１層目の金属配線を周辺回路に、２層
目の金属配線を電源配線部のみに使用することにより、
電源配線部面積を大きく取り、寄生抵抗を低減したので
、ノイズによる誤動作の起こりにくい安定した半導体装
置を得ることができる。As described above, according to the present invention, by using the first layer metal wiring of a semiconductor device having a two-layer metal wiring configuration for the peripheral circuit and the second layer metal wiring only for the power supply wiring part,
Since the area of the power supply wiring portion is large and the parasitic resistance is reduced, a stable semiconductor device that is less likely to malfunction due to noise can be obtained.
第１図はこの発明の一実施例を示す半導体メモリ装置の
チップ平面図、第２図は従来の半導体メモリ装置のチッ
プの平面図、第３図はノイズ不良の発生メカニズムを示
す説明図、第４図は従来およびこの発明の各信号の波形
図である。
図において、ｌはＩＣチップ、２はメモリセルアレイ、
及びデータを伝達する信号配線、３はＶ ｃｃバンド、
４はＧＮＤパフド、５はｖｃｃ配線、６はＧＮＤ配線、
７はＶ ｃｃ側周辺回路、８はＧＮＤ側周辺回路、９．
１０はＶ ｃｃ側周辺回路に含まれる反転回路、（ａｌ
は反転回路１０の人力、（ｂｌは反転回路９の入力、Ｒ
はＧＮＤ配ｖＡ６の寄生抵抗値、図中、斜線部は２層目
の金属配線使用部を示す。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a plan view of a chip of a semiconductor memory device showing an embodiment of the present invention, FIG. 2 is a plan view of a chip of a conventional semiconductor memory device, FIG. FIG. 4 is a waveform diagram of each signal of the conventional method and the present invention. In the figure, l is an IC chip, 2 is a memory cell array,
and signal wiring for transmitting data; 3 is a Vcc band;
4 is GND puffed, 5 is VCC wiring, 6 is GND wiring,
7 is a Vcc side peripheral circuit, 8 is a GND side peripheral circuit, 9.
10 is an inverting circuit included in the peripheral circuit on the Vcc side, (al
is the manual power of the inverting circuit 10, (bl is the input of the inverting circuit 9, R
is the parasitic resistance value of the GND wiring vA6, and the shaded area in the figure shows the part where the second layer metal wiring is used. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
金属配線を周辺回路部に、２層目の金属配線を電源配線
部にのみ使用することを特徴とする半導体装置。A semiconductor device comprising two layers of metal wiring, characterized in that the first layer of metal wiring is used only for a peripheral circuit section, and the second layer of metal wiring is used only for a power supply wiring section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1170263A JPH0335496A (en) | 1989-06-30 | 1989-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1170263A JPH0335496A (en) | 1989-06-30 | 1989-06-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0335496A true JPH0335496A (en) | 1991-02-15 |
Family
ID=15901696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1170263A Pending JPH0335496A (en) | 1989-06-30 | 1989-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0335496A (en) |
-
1989
- 1989-06-30 JP JP1170263A patent/JPH0335496A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0621320A (en) | Semiconductor integrated circuit device | |
| JPS64822B2 (en) | ||
| JPH0126511B2 (en) | ||
| JPS5840344B2 (en) | semiconductor storage device | |
| JPH0335496A (en) | Semiconductor device | |
| JPH0212027B2 (en) | ||
| JPH03148827A (en) | Semiconductor integrated circuit | |
| JPH0786526A (en) | Memory device | |
| JPS61148854A (en) | Lead frame | |
| JPS6077436A (en) | Semiconductor integrated circuit | |
| JPS6161256B2 (en) | ||
| JPH0419633B2 (en) | ||
| JP2829994B2 (en) | Semiconductor integrated circuit | |
| JPS6074554A (en) | Large scale integrated circuit | |
| JP2900555B2 (en) | Semiconductor integrated circuit | |
| JPH0110936Y2 (en) | ||
| JPH04171843A (en) | Gate array system lsi | |
| JPH02264432A (en) | Semiconductor device | |
| JP3184384B2 (en) | Semiconductor device | |
| JP2518253B2 (en) | Semiconductor integrated circuit and manufacturing method thereof | |
| JPH03236236A (en) | Semiconductor integrated circuit device | |
| JPS63221712A (en) | Semiconductor integrated circuit device | |
| JPH01308061A (en) | Semiconductor device | |
| JPS6028257A (en) | Integrated circuit | |
| KR20000041579A (en) | Semiconductor memory device having selective bonding option pads |