JPH01308061A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress a noise due to a capacity CBB between wirings even in a reduced semiconductor device by specifying the capacity CBB by wirings to be floated at the time of the operation of a circuit. CONSTITUTION:In a semiconductor device in which certain wirings become an operation mode becoming a high impedance state of 10MOMEGA or more, i.e., a floating state with preceding and following circuits in a certain time width within the operating time of the device, the ratio CBB/CB of a parasitic capacity CBB between the wirings to a parasitic capacity CB between the wirings becoming a floating state and a board is set to 0.1 or less. If CBB1=0.1CB is employed as an example of satisfying the condition of XBB1<=0.1CB, when a wiring interval is simply reduced to d1, a capacity CBB2 becomes twice as large as the CBB1, i.e., it receives the influence of the potential change of adjacent wiring twice as large as that. Then, if the thickness (t) of the wiring becoming the floating state is t1, the condition of CBB3 <=0.1CB can be satisfied.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体デバイスの動作時において、配線間の寄
生容量に起因するノイズを動作に支障を生じさせないレ
ベルに抑制することができる半導体デバイスに関するも
のである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device that can suppress noise caused by parasitic capacitance between wiring lines to a level that does not interfere with the operation of the semiconductor device. It is something.

〔従来の技術〕[Conventional technology]

従来の半導体デバイスにセいては配線の膜厚は主にエレ
クトロマイグレーション対策のために、電流密度を下げ
るため一般に厚めに設定されていた。In conventional semiconductor devices, the film thickness of interconnections has generally been set thick to reduce current density, mainly as a countermeasure against electromigration.

第２図は従来の半導体デバイスの一例を示したもので、
図において、（１）はフローティング状態となる配線、
（２）は配線（１）の隣接配＠、（３７は配線＋１１　
＋２１が設けられた基板である。＠３図は第２図の半導
体デバイスの等価回路図を示す。Figure 2 shows an example of a conventional semiconductor device.
In the figure, (1) is a wiring that is in a floating state;
(2) is the wiring adjacent to wiring (1) @, (37 is wiring + 11
This is a board on which +21 is provided. @Figure 3 shows an equivalent circuit diagram of the semiconductor device of Figure 2.

ところが配線（１１＋２１間の容量ＣＢＢは配線の膜厚
ｔと配線長ｌ及び配線間隔ｄのパラメータに対して、Ｃ
ＢＩＩ　ｃｔ旦 の関係にある。However, the capacitance CBB between the wiring (11+21) is C
It is related to BII CT.

従がって、半導体デバイスが微細化され配線間隔ｄがサ
ブミクロン領域となると、容量Ｃｎｎが非常に大きくな
ってくるので隣接する配線ｆｉｌ　＋２１の電位の影響
を強く受ける結果となる。Therefore, when semiconductor devices are miniaturized and the wiring spacing d reaches the submicron range, the capacitance Cnn becomes extremely large and is therefore strongly influenced by the potential of the adjacent wiring fil +21.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体デバイスは以上のように構成されているの
で、縮小化に際して配線間の寄生容量によるノイズによ
る影響を無視することができず、その対策が問題であっ
た。Since conventional semiconductor devices are configured as described above, the influence of noise due to parasitic capacitance between wirings cannot be ignored when downsizing, and countermeasures have been a problem.

本発明は半導体デバイスの縮小化に伴ない配線のデイメ
ンジオンに対しても、比例縮小期を導入し、隣接する配
線からのノイズを受けやすく配線レイヤーに対して配線
間隔ｄの縮小に対してｔも等価に縮小し、寄生容ｆＪｔ
ｃＢＢの増大を防ぎ、回路動作において寄先容：ｌ　Ｃ
ｎｎによるノイズの影響を受けない半導体デバイスを得
る事を目的としている。The present invention also introduces a proportional reduction period for wiring dimensions as semiconductor devices become smaller. Reduced equivalently, the parasitic capacitance fJt
It prevents the increase of cBB and reduces the capacitance: l C in circuit operation.
The objective is to obtain a semiconductor device that is not affected by noise caused by nn.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は半導体デバイスにおいて回路動作時にフローテ
ィングとなる配線で、配線間容［ＣｎｎをＣＢＩＩ　／
Ｃｎ　ｌ　０．１　　とする事により、縮小化された半
導体デバイスにおいてもＣｎｎに起因するノイズを抑制
するものである。The present invention relates to wiring that becomes floating during circuit operation in a semiconductor device, and the wiring spacing [Cnn is CBII /
By setting Cn l 0.1, noise caused by Cnn can be suppressed even in a downsized semiconductor device.

〔作用〕 本発明Ｉこおける半導体デバイスはフローティング状態
となったある配線の電位が隣接する配線の電位に寄生容
ｆｉ　Ｃｎｎを介して影響を受けない、すなわち、配線
の電位が変動しない事である。[Function] In the semiconductor device according to the present invention I, the potential of a certain wiring in a floating state is not affected by the potential of an adjacent wiring via the parasitic capacitance, that is, the potential of the wiring does not change. .

〔実施例〕〔Example〕

以下２本発明の一実施例を図に基づいて説明する。なお
、図中符号（１）〜（３）およびＣＩＩＢ、Ｃ１１，／
、ｄ、ｔは前記従来のものと同一につき説明は省略する
。Hereinafter, two embodiments of the present invention will be described based on the drawings. In addition, symbols (1) to (3) in the figure and CIIB, C11, /
, d, and t are the same as those of the prior art, so their explanation will be omitted.

＠４図は従来のデバイスサイズを示す斜視図で、この時
。@Figure 4 is a perspective view showing the conventional device size.

ＣＢＢＩイｏ、　ｔ　Ｃｎ の条件を満たす例として　ＣＩＩＢＩ　＝ｍ＝　０．　
Ｉ　Ｃｎ　　とすると、配線間隔ｄｌを単純に縮小する
と、第１図（ａ）の如く寄生容（１ｔｃｎｎｍ　　はＣ
ｎｎｔ　　の２倍となり、すなわち隣接する配線１２）
の電位変動の影響を２倍強く受ける事となる。As an example that satisfies the conditions of CBBIio, tCn, CIIBI=m=0.
If I Cn is simply reduced, the parasitic capacitance (1tcnnm is C
nnt, that is, the adjacent wiring 12)
It will be twice as strongly affected by potential fluctuations.

そこで第１図（ｂ）の如く、配線（１）の膜厚ｔを　ｔ
ｌとすれば　Ｃｎｎ３１０．１　ＣＢの条件を満たす事
が出来る。Therefore, as shown in Figure 1(b), the film thickness t of the wiring (1) is t
If it is 1, the condition of Cnn310.1 CB can be satisfied.

この時は当然配線抵抗Ｒが２倍となる事及び電流密度も
２倍となるが、配線の埜料を適切に選ぶ事により、これ
らの障害を取り除く事は充分に可能である。In this case, of course, the wiring resistance R is doubled and the current density is also doubled, but it is fully possible to eliminate these obstacles by appropriately selecting the wiring material.

本発明はある配線イ１）が−時的にフローティング状態
となる動作モードをもつような半導体デバイスにおいて
はすべての配線に適用することが可能であることはいう
までもない。It goes without saying that the present invention can be applied to all wiring in a semiconductor device in which a certain wiring (1) has an operation mode in which it is temporarily in a floating state.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、半導体デバイスを縮小し
ても配線間の寄生容措によるノイズを抑制が出来従がっ
て、安定した動作余裕を有する事が出来る効果がある。As described above, according to the present invention, even if the semiconductor device is reduced in size, noise due to parasitic interference between wirings can be suppressed, and therefore, it is possible to have a stable operating margin.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）（ｂ）は本発明の一実施例を示す半導体デ
バイスの説明斜視図、第２図は従来の半導体デ、（イス
の説明斜視図、第３図は第２図に示すものの等価回路図
、ｆｆ１４１’Ｎは第１図に示すものに対応させて従来
の半導体デバイスを説明する斜視図である。 （１）はフローティング状態となる配線、（２）は隣接
する配線、（３）は基板を示す。 なお、図中、同一符号は同一、または相当部分を示す。1(a) and (b) are explanatory perspective views of a semiconductor device showing one embodiment of the present invention, FIG. 2 is an explanatory perspective view of a conventional semiconductor device (chair), and FIG. ff141'N is a perspective view illustrating a conventional semiconductor device corresponding to that shown in Fig. 1. (1) is a wiring in a floating state, (2) is an adjacent wiring, ( 3) indicates a substrate. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 　半導体デバイスの動作時間内のある時間幅において、
ある配線が前後の回路と１０ＭΩ以上の高いインピーダ
ンス状態となるすなわちフローティング状態となる動作
モードを有する半導体デバイスにおいて、フローティン
グ状態となる配線の基板との間の寄生容量Ｃ＿Ｂと配線
間の奇生容量Ｃ＿Ｂ＿Ｂの比率Ｃ＿Ｂ＿Ｂ／Ｃ＿Ｂが０
．１以下であることを特徴とする半導体デバイス。During a certain time span within the operating time of a semiconductor device,
In a semiconductor device that has an operation mode in which a certain wiring is in a high impedance state of 10 MΩ or more with the circuits before and after it, that is, in a floating state, the parasitic capacitance C_B between the floating wiring and the substrate and the parasitic capacitance C_B_B between the wirings. The ratio C_B_B/C_B is 0
．． 1 or less.