JPH01308061A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01308061A JPH01308061A JP13965088A JP13965088A JPH01308061A JP H01308061 A JPH01308061 A JP H01308061A JP 13965088 A JP13965088 A JP 13965088A JP 13965088 A JP13965088 A JP 13965088A JP H01308061 A JPH01308061 A JP H01308061A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wirings
- semiconductor device
- cbb
- capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 230000003071 parasitic effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 2
- 101100063431 Arabidopsis thaliana DIM gene Proteins 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体デバイスの動作時において、配線間の寄
生容量に起因するノイズを動作に支障を生じさせないレ
ベルに抑制することができる半導体デバイスに関するも
のである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device that can suppress noise caused by parasitic capacitance between wiring lines to a level that does not interfere with the operation of the semiconductor device. It is something.
従来の半導体デバイスにセいては配線の膜厚は主にエレ
クトロマイグレーション対策のために、電流密度を下げ
るため一般に厚めに設定されていた。In conventional semiconductor devices, the film thickness of interconnections has generally been set thick to reduce current density, mainly as a countermeasure against electromigration.
第2図は従来の半導体デバイスの一例を示したもので、
図において、(1)はフローティング状態となる配線、
(2)は配線(1)の隣接配@、(37は配線+11
+21が設けられた基板である。@3図は第2図の半導
体デバイスの等価回路図を示す。Figure 2 shows an example of a conventional semiconductor device.
In the figure, (1) is a wiring that is in a floating state;
(2) is the wiring adjacent to wiring (1) @, (37 is wiring + 11
This is a board on which +21 is provided. @Figure 3 shows an equivalent circuit diagram of the semiconductor device of Figure 2.
ところが配線(11+21間の容量CBBは配線の膜厚
tと配線長l及び配線間隔dのパラメータに対して、C
BII ct旦
の関係にある。However, the capacitance CBB between the wiring (11+21) is C
It is related to BII CT.
従がって、半導体デバイスが微細化され配線間隔dがサ
ブミクロン領域となると、容量Cnnが非常に大きくな
ってくるので隣接する配線fil +21の電位の影響
を強く受ける結果となる。Therefore, when semiconductor devices are miniaturized and the wiring spacing d reaches the submicron range, the capacitance Cnn becomes extremely large and is therefore strongly influenced by the potential of the adjacent wiring fil +21.
従来の半導体デバイスは以上のように構成されているの
で、縮小化に際して配線間の寄生容量によるノイズによ
る影響を無視することができず、その対策が問題であっ
た。Since conventional semiconductor devices are configured as described above, the influence of noise due to parasitic capacitance between wirings cannot be ignored when downsizing, and countermeasures have been a problem.
本発明は半導体デバイスの縮小化に伴ない配線のデイメ
ンジオンに対しても、比例縮小期を導入し、隣接する配
線からのノイズを受けやすく配線レイヤーに対して配線
間隔dの縮小に対してtも等価に縮小し、寄生容fJt
cBBの増大を防ぎ、回路動作において寄先容:l C
nnによるノイズの影響を受けない半導体デバイスを得
る事を目的としている。The present invention also introduces a proportional reduction period for wiring dimensions as semiconductor devices become smaller. Reduced equivalently, the parasitic capacitance fJt
It prevents the increase of cBB and reduces the capacitance: l C in circuit operation.
The objective is to obtain a semiconductor device that is not affected by noise caused by nn.
本発明は半導体デバイスにおいて回路動作時にフローテ
ィングとなる配線で、配線間容[CnnをCBII /
Cn l 0.1 とする事により、縮小化された半
導体デバイスにおいてもCnnに起因するノイズを抑制
するものである。The present invention relates to wiring that becomes floating during circuit operation in a semiconductor device, and the wiring spacing [Cnn is CBII /
By setting Cn l 0.1, noise caused by Cnn can be suppressed even in a downsized semiconductor device.
〔作用〕
本発明Iこおける半導体デバイスはフローティング状態
となったある配線の電位が隣接する配線の電位に寄生容
fi Cnnを介して影響を受けない、すなわち、配線
の電位が変動しない事である。[Function] In the semiconductor device according to the present invention I, the potential of a certain wiring in a floating state is not affected by the potential of an adjacent wiring via the parasitic capacitance, that is, the potential of the wiring does not change. .
以下2本発明の一実施例を図に基づいて説明する。なお
、図中符号(1)〜(3)およびCIIB、C11,/
、d、tは前記従来のものと同一につき説明は省略する
。Hereinafter, two embodiments of the present invention will be described based on the drawings. In addition, symbols (1) to (3) in the figure and CIIB, C11, /
, d, and t are the same as those of the prior art, so their explanation will be omitted.
@4図は従来のデバイスサイズを示す斜視図で、この時
。@Figure 4 is a perspective view showing the conventional device size.
CBBIイo、 t Cn
の条件を満たす例として CIIBI =m= 0.
I Cn とすると、配線間隔dlを単純に縮小する
と、第1図(a)の如く寄生容(1tcnnm はC
nnt の2倍となり、すなわち隣接する配線12)
の電位変動の影響を2倍強く受ける事となる。As an example that satisfies the conditions of CBBIio, tCn, CIIBI=m=0.
If I Cn is simply reduced, the parasitic capacitance (1tcnnm is C
nnt, that is, the adjacent wiring 12)
It will be twice as strongly affected by potential fluctuations.
そこで第1図(b)の如く、配線(1)の膜厚tを t
lとすれば Cnn310.1 CBの条件を満たす事
が出来る。Therefore, as shown in Figure 1(b), the film thickness t of the wiring (1) is t
If it is 1, the condition of Cnn310.1 CB can be satisfied.
この時は当然配線抵抗Rが2倍となる事及び電流密度も
2倍となるが、配線の埜料を適切に選ぶ事により、これ
らの障害を取り除く事は充分に可能である。In this case, of course, the wiring resistance R is doubled and the current density is also doubled, but it is fully possible to eliminate these obstacles by appropriately selecting the wiring material.
本発明はある配線イ1)が−時的にフローティング状態
となる動作モードをもつような半導体デバイスにおいて
はすべての配線に適用することが可能であることはいう
までもない。It goes without saying that the present invention can be applied to all wiring in a semiconductor device in which a certain wiring (1) has an operation mode in which it is temporarily in a floating state.
以上のように本発明によれば、半導体デバイスを縮小し
ても配線間の寄生容措によるノイズを抑制が出来従がっ
て、安定した動作余裕を有する事が出来る効果がある。As described above, according to the present invention, even if the semiconductor device is reduced in size, noise due to parasitic interference between wirings can be suppressed, and therefore, it is possible to have a stable operating margin.
第1図(a)(b)は本発明の一実施例を示す半導体デ
バイスの説明斜視図、第2図は従来の半導体デ、(イス
の説明斜視図、第3図は第2図に示すものの等価回路図
、ff141’Nは第1図に示すものに対応させて従来
の半導体デバイスを説明する斜視図である。
(1)はフローティング状態となる配線、(2)は隣接
する配線、(3)は基板を示す。
なお、図中、同一符号は同一、または相当部分を示す。1(a) and (b) are explanatory perspective views of a semiconductor device showing one embodiment of the present invention, FIG. 2 is an explanatory perspective view of a conventional semiconductor device (chair), and FIG. ff141'N is a perspective view illustrating a conventional semiconductor device corresponding to that shown in Fig. 1. (1) is a wiring in a floating state, (2) is an adjacent wiring, ( 3) indicates a substrate. In the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ある配線が前後の回路と10MΩ以上の高いインピーダ
ンス状態となるすなわちフローティング状態となる動作
モードを有する半導体デバイスにおいて、フローティン
グ状態となる配線の基板との間の寄生容量C_Bと配線
間の奇生容量C_B_Bの比率C_B_B/C_Bが0
.1以下であることを特徴とする半導体デバイス。During a certain time span within the operating time of a semiconductor device,
In a semiconductor device that has an operation mode in which a certain wiring is in a high impedance state of 10 MΩ or more with the circuits before and after it, that is, in a floating state, the parasitic capacitance C_B between the floating wiring and the substrate and the parasitic capacitance C_B_B between the wirings. The ratio C_B_B/C_B is 0
.. 1 or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13965088A JP2687442B2 (en) | 1988-06-06 | 1988-06-06 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13965088A JP2687442B2 (en) | 1988-06-06 | 1988-06-06 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01308061A true JPH01308061A (en) | 1989-12-12 |
JP2687442B2 JP2687442B2 (en) | 1997-12-08 |
Family
ID=15250211
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13965088A Expired - Lifetime JP2687442B2 (en) | 1988-06-06 | 1988-06-06 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2687442B2 (en) |
-
1988
- 1988-06-06 JP JP13965088A patent/JP2687442B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2687442B2 (en) | 1997-12-08 |
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