JPH04171843A - Gate array system lsi - Google Patents
Gate array system lsiInfo
- Publication number
- JPH04171843A JPH04171843A JP2299527A JP29952790A JPH04171843A JP H04171843 A JPH04171843 A JP H04171843A JP 2299527 A JP2299527 A JP 2299527A JP 29952790 A JP29952790 A JP 29952790A JP H04171843 A JPH04171843 A JP H04171843A
- Authority
- JP
- Japan
- Prior art keywords
- gnd
- bonding pad
- current
- flow
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052782 aluminium Inorganic materials 0.000 abstract description 10
- 239000000872 buffer Substances 0.000 abstract description 6
- 230000007257 malfunction Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ゲートアレイ方式LSIに関し、特に未使用
ボンディングパットのGNDパット化に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array type LSI, and particularly to converting an unused bonding pad into a GND pad.
従来の未使用ボンディングパットは第3図に示すように
、LSIテスター上での測定時にはテスターのGNDに
接続されていない。As shown in FIG. 3, conventional unused bonding pads are not connected to the GND of the tester during measurement on the LSI tester.
また、未使用ボンディングパットをGNDバットとして
利用した場合でも、LSIテスターの治具上の制約によ
りLSIテスターのGND線には接続されていない。Further, even if an unused bonding pad is used as a GND bat, it is not connected to the GND line of the LSI tester due to restrictions on the LSI tester jig.
上述した従来のゲートアレイ方式LSIは、外部出力バ
ッファの同時動作など、GND線に集中的に電流が流れ
る場合、基板電圧の電圧レベルの上昇によりLSIの誤
動作を起す問題点があった。The conventional gate array type LSI described above has a problem in that when a current flows intensively to the GND line due to simultaneous operation of external output buffers, the voltage level of the substrate voltage rises, causing malfunction of the LSI.
本発明の目的は、LSIの誤動作を低減するゲートアレ
イ方式LSIを提供することにある。An object of the present invention is to provide a gate array type LSI that reduces malfunctions of the LSI.
本発明のゲートアレイ方式LSIは、未使用ボンディン
グパットを有する場合に、GNDパットと未使用ボンデ
ィングパット間を配線接続し、未使用ボンディングパッ
トをGNDパットとして扱い、GND線上の電流を分散
して流し多電流が流れる場合に発生する誤動作を低減さ
せる機能を備えている。When the gate array type LSI of the present invention has an unused bonding pad, the GND pad and the unused bonding pad are connected by wiring, the unused bonding pad is treated as a GND pad, and the current on the GND line is distributed and passed. It has a function that reduces malfunctions that occur when large amounts of current flow.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は、本発明の一実施例の構成図である。第1図に
示すように、未使用ボンディングパットが存在する場合
には、GNDパットlがら内部バッファ領域までの第1
アルミ配!!4の間にスルーホール3をつくる。FIG. 1 is a configuration diagram of an embodiment of the present invention. As shown in FIG. 1, if there is an unused bonding pad, the first
Aluminum distribution! ! Make through hole 3 between 4.
第2アルミ配線5で未使用ボンディングパット2から内
部バッファ領域までの第1アルミ配線4に接続すること
で、従来例18.〈チップ図面)第3図のGND線16
がらの電流は、未使用ボンディングパット13がらは電
流を分散して、テスターのGNDに流すことができない
。これに対し、第1図のGND線6がらの電流は、Aが
らB電流れGNDバットを通りテスターのGNDへ流れ
る。このように、電流を分散して流すことができる。By connecting the second aluminum wiring 5 to the first aluminum wiring 4 from the unused bonding pad 2 to the internal buffer area, conventional example 18. (Chip drawing) GND line 16 in Figure 3
The current from the unused bonding pad 13 is dispersed and cannot be passed to the GND of the tester. On the other hand, the current from the GND wire 6 in FIG. 1 flows from A to B through the GND bat to the GND of the tester. In this way, current can be distributed in a distributed manner.
第2図は本発明の第2の実施例を示す構成図である。G
NDパット7がら未使用ボンディングパット8にバット
の外側をアルミ配線することによりGND線11からの
電流はAからBに流れ、GNDパットを通りテスターの
GNDへ流れるので電流を分散して流すことができる。FIG. 2 is a block diagram showing a second embodiment of the present invention. G
By wiring the outside of the bat from the ND pad 7 to the unused bonding pad 8, the current from the GND wire 11 flows from A to B, passes through the GND pad, and flows to the GND of the tester, so the current can be distributed in a distributed manner. can.
以上説明したように本発明は、GNDパットと、未使用
ボンディングパットを配線して、その未使用ボンディン
グパットをGND線上に配線する。この方法により、外
部出力バッファの同時動作などが発生し、多電流がGN
D線上に流れる場合、その電流を分散する機能を果す。As described above, in the present invention, a GND pad and an unused bonding pad are wired, and the unused bonding pad is wired on the GND line. With this method, simultaneous operation of external output buffers, etc. occurs, and multiple currents are
When flowing on the D line, it functions to disperse the current.
これは未使用ボンイングバットをGNDパットとして扱
うことによりLSIが誤動作することを低減する効果を
有する。This has the effect of reducing malfunctions of the LSI by treating an unused bong bat as a GND pad.
第1図は本発明の一実施例の平面図、第2図は本発明の
他の実施例の平面図、第3図は従来例を示す平面図であ
る。
1・・・GNDパット、2・・・未使用ボンディングパ
ット、3・・・スルーホール、4・・・第1アルミ、5
・・・第2アルミ、6・・・GND線、7・・・GND
バット、8・・・未使用ボンディングパット、9・・・
スルーホール、10・・・第1アルミ、11・・・GN
D線、12・・・GNDパット、13・・・未使用ボン
ディングパット、14・・・スルーホール、15・・・
第1アルミ、16・・・GND線、17・・・内部セル
、18・・・チップ図面。FIG. 1 is a plan view of one embodiment of the invention, FIG. 2 is a plan view of another embodiment of the invention, and FIG. 3 is a plan view of a conventional example. 1... GND pad, 2... Unused bonding pad, 3... Through hole, 4... First aluminum, 5
...Second aluminum, 6...GND line, 7...GND
Bat, 8...Unused bonding pad, 9...
Through hole, 10...1st aluminum, 11...GN
D line, 12... GND pad, 13... Unused bonding pad, 14... Through hole, 15...
1st aluminum, 16... GND line, 17... internal cell, 18... chip drawing.
Claims (1)
続し、前記未使用ボンディングパットをGNDパットと
したことを特徴とするゲートアレイ方式LSI。A gate array type LSI characterized in that a GND pad and an unused bonding pad are connected by wiring, and the unused bonding pad is used as a GND pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2299527A JPH04171843A (en) | 1990-11-05 | 1990-11-05 | Gate array system lsi |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2299527A JPH04171843A (en) | 1990-11-05 | 1990-11-05 | Gate array system lsi |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04171843A true JPH04171843A (en) | 1992-06-19 |
Family
ID=17873755
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2299527A Pending JPH04171843A (en) | 1990-11-05 | 1990-11-05 | Gate array system lsi |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04171843A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6130484A (en) * | 1997-07-17 | 2000-10-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
JP2007227780A (en) * | 2006-02-24 | 2007-09-06 | Alps Electric Co Ltd | Wiring structure of semiconductor component |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01168042A (en) * | 1987-12-23 | 1989-07-03 | Sharp Corp | Semiconductor integrated circuit device |
JPH0364045A (en) * | 1989-08-02 | 1991-03-19 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1990
- 1990-11-05 JP JP2299527A patent/JPH04171843A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01168042A (en) * | 1987-12-23 | 1989-07-03 | Sharp Corp | Semiconductor integrated circuit device |
JPH0364045A (en) * | 1989-08-02 | 1991-03-19 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6130484A (en) * | 1997-07-17 | 2000-10-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
KR100282973B1 (en) * | 1997-07-17 | 2001-04-02 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device |
JP2007227780A (en) * | 2006-02-24 | 2007-09-06 | Alps Electric Co Ltd | Wiring structure of semiconductor component |
JP4685660B2 (en) * | 2006-02-24 | 2011-05-18 | アルプス電気株式会社 | Wiring structure of semiconductor parts |
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