JPH04171843A - Gate array system lsi - Google Patents

Gate array system lsi

Info

Publication number
JPH04171843A
JPH04171843A JP2299527A JP29952790A JPH04171843A JP H04171843 A JPH04171843 A JP H04171843A JP 2299527 A JP2299527 A JP 2299527A JP 29952790 A JP29952790 A JP 29952790A JP H04171843 A JPH04171843 A JP H04171843A
Authority
JP
Japan
Prior art keywords
gnd
bonding pad
current
flow
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2299527A
Other languages
Japanese (ja)
Inventor
Masaharu Tomizawa
冨澤　正治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP2299527A priority Critical patent/JPH04171843A/en
Publication of JPH04171843A publication Critical patent/JPH04171843A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To make a current through a GND conductor flow dispersedly and to reduce the malfunction of an LSI, which is generated in the case a multicurrent flows, by a method wherein GND pads and an unused bonding pad are connected to each other via wiring and the unused bonding pad is used as a GND pad. CONSTITUTION:In the case an unused bonding pad exists, through holes 3 are respectively formed in first aluminum wirings 4 between GND pads 1 and an internal buffer region. The wiring 4 is connected to first aluminum wiring 4 between the unused bonding pad 2 and the internal buffer region via second aluminum wiring 5, whereby a current from a GND conductor 6 passes through the GND pads so as to flow from A to B, is made to flow to a GND of a tester and the current can dispersedly be made to flow. Thereby, the simultaneous operation of an external output buffer or the like is generated, the current in the case a multicurrent is made to flow through the GND conductor is dispersed and the generation of the malfunction of an LSI is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ゲートアレイ方式ＬＳＩに関し、特に未使用
ボンディングパットのＧＮＤパット化に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array type LSI, and particularly to converting an unused bonding pad into a GND pad.

〔従来の技術〕[Conventional technology]

従来の未使用ボンディングパットは第３図に示すように
、ＬＳＩテスター上での測定時にはテスターのＧＮＤに
接続されていない。As shown in FIG. 3, conventional unused bonding pads are not connected to the GND of the tester during measurement on the LSI tester.

また、未使用ボンディングパットをＧＮＤバットとして
利用した場合でも、ＬＳＩテスターの治具上の制約によ
りＬＳＩテスターのＧＮＤ線には接続されていない。Further, even if an unused bonding pad is used as a GND bat, it is not connected to the GND line of the LSI tester due to restrictions on the LSI tester jig.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のゲートアレイ方式ＬＳＩは、外部出力バ
ッファの同時動作など、ＧＮＤ線に集中的に電流が流れ
る場合、基板電圧の電圧レベルの上昇によりＬＳＩの誤
動作を起す問題点があった。The conventional gate array type LSI described above has a problem in that when a current flows intensively to the GND line due to simultaneous operation of external output buffers, the voltage level of the substrate voltage rises, causing malfunction of the LSI.

本発明の目的は、ＬＳＩの誤動作を低減するゲートアレ
イ方式ＬＳＩを提供することにある。An object of the present invention is to provide a gate array type LSI that reduces malfunctions of the LSI.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のゲートアレイ方式ＬＳＩは、未使用ボンディン
グパットを有する場合に、ＧＮＤパットと未使用ボンデ
ィングパット間を配線接続し、未使用ボンディングパッ
トをＧＮＤパットとして扱い、ＧＮＤ線上の電流を分散
して流し多電流が流れる場合に発生する誤動作を低減さ
せる機能を備えている。When the gate array type LSI of the present invention has an unused bonding pad, the GND pad and the unused bonding pad are connected by wiring, the unused bonding pad is treated as a GND pad, and the current on the GND line is distributed and passed. It has a function that reduces malfunctions that occur when large amounts of current flow.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は、本発明の一実施例の構成図である。第１図に
示すように、未使用ボンディングパットが存在する場合
には、ＧＮＤパットｌがら内部バッファ領域までの第１
アルミ配！！４の間にスルーホール３をつくる。FIG. 1 is a configuration diagram of an embodiment of the present invention. As shown in FIG. 1, if there is an unused bonding pad, the first
Aluminum distribution! ! Make through hole 3 between 4.

第２アルミ配線５で未使用ボンディングパット２から内
部バッファ領域までの第１アルミ配線４に接続すること
で、従来例１８．〈チップ図面）第３図のＧＮＤ線１６
がらの電流は、未使用ボンディングパット１３がらは電
流を分散して、テスターのＧＮＤに流すことができない
。これに対し、第１図のＧＮＤ線６がらの電流は、Ａが
らＢ電流れＧＮＤバットを通りテスターのＧＮＤへ流れ
る。このように、電流を分散して流すことができる。By connecting the second aluminum wiring 5 to the first aluminum wiring 4 from the unused bonding pad 2 to the internal buffer area, conventional example 18. (Chip drawing) GND line 16 in Figure 3
The current from the unused bonding pad 13 is dispersed and cannot be passed to the GND of the tester. On the other hand, the current from the GND wire 6 in FIG. 1 flows from A to B through the GND bat to the GND of the tester. In this way, current can be distributed in a distributed manner.

第２図は本発明の第２の実施例を示す構成図である。Ｇ
ＮＤパット７がら未使用ボンディングパット８にバット
の外側をアルミ配線することによりＧＮＤ線１１からの
電流はＡからＢに流れ、ＧＮＤパットを通りテスターの
ＧＮＤへ流れるので電流を分散して流すことができる。FIG. 2 is a block diagram showing a second embodiment of the present invention. G
By wiring the outside of the bat from the ND pad 7 to the unused bonding pad 8, the current from the GND wire 11 flows from A to B, passes through the GND pad, and flows to the GND of the tester, so the current can be distributed in a distributed manner. can.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＧＮＤパットと、未使用
ボンディングパットを配線して、その未使用ボンディン
グパットをＧＮＤ線上に配線する。この方法により、外
部出力バッファの同時動作などが発生し、多電流がＧＮ
Ｄ線上に流れる場合、その電流を分散する機能を果す。As described above, in the present invention, a GND pad and an unused bonding pad are wired, and the unused bonding pad is wired on the GND line. With this method, simultaneous operation of external output buffers, etc. occurs, and multiple currents are
When flowing on the D line, it functions to disperse the current.

これは未使用ボンイングバットをＧＮＤパットとして扱
うことによりＬＳＩが誤動作することを低減する効果を
有する。This has the effect of reducing malfunctions of the LSI by treating an unused bong bat as a GND pad.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の平面図、第２図は本発明の
他の実施例の平面図、第３図は従来例を示す平面図であ
る。 １・・・ＧＮＤパット、２・・・未使用ボンディングパ
ット、３・・・スルーホール、４・・・第１アルミ、５
・・・第２アルミ、６・・・ＧＮＤ線、７・・・ＧＮＤ
バット、８・・・未使用ボンディングパット、９・・・
スルーホール、１０・・・第１アルミ、１１・・・ＧＮ
Ｄ線、１２・・・ＧＮＤパット、１３・・・未使用ボン
ディングパット、１４・・・スルーホール、１５・・・
第１アルミ、１６・・・ＧＮＤ線、１７・・・内部セル
、１８・・・チップ図面。FIG. 1 is a plan view of one embodiment of the invention, FIG. 2 is a plan view of another embodiment of the invention, and FIG. 3 is a plan view of a conventional example. 1... GND pad, 2... Unused bonding pad, 3... Through hole, 4... First aluminum, 5
...Second aluminum, 6...GND line, 7...GND
Bat, 8...Unused bonding pad, 9...
Through hole, 10...1st aluminum, 11...GN
D line, 12... GND pad, 13... Unused bonding pad, 14... Through hole, 15...
1st aluminum, 16... GND line, 17... internal cell, 18... chip drawing.

Claims (1)

【特許請求の範囲】[Claims] 　ＧＮＤパットと未使用ボンディングパット間を配線接
続し、前記未使用ボンディングパットをＧＮＤパットと
したことを特徴とするゲートアレイ方式ＬＳＩ。A gate array type LSI characterized in that a GND pad and an unused bonding pad are connected by wiring, and the unused bonding pad is used as a GND pad.
JP2299527A 1990-11-05 1990-11-05 Gate array system lsi Pending JPH04171843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2299527A JPH04171843A (en) 1990-11-05 1990-11-05 Gate array system lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2299527A JPH04171843A (en) 1990-11-05 1990-11-05 Gate array system lsi

Publications (1)

Publication Number Publication Date
JPH04171843A true JPH04171843A (en) 1992-06-19

Family

ID=17873755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2299527A Pending JPH04171843A (en) 1990-11-05 1990-11-05 Gate array system lsi

Country Status (1)

Country Link
JP (1) JPH04171843A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130484A (en) * 1997-07-17 2000-10-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2007227780A (en) * 2006-02-24 2007-09-06 Alps Electric Co Ltd Wiring structure of semiconductor component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01168042A (en) * 1987-12-23 1989-07-03 Sharp Corp Semiconductor integrated circuit device
JPH0364045A (en) * 1989-08-02 1991-03-19 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01168042A (en) * 1987-12-23 1989-07-03 Sharp Corp Semiconductor integrated circuit device
JPH0364045A (en) * 1989-08-02 1991-03-19 Hitachi Ltd Semiconductor integrated circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130484A (en) * 1997-07-17 2000-10-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR100282973B1 (en) * 1997-07-17 2001-04-02 다니구찌 이찌로오, 기타오카 다카시 Semiconductor device
JP2007227780A (en) * 2006-02-24 2007-09-06 Alps Electric Co Ltd Wiring structure of semiconductor component
JP4685660B2 (en) * 2006-02-24 2011-05-18 アルプス電気株式会社 Wiring structure of semiconductor parts

Similar Documents

Publication Publication Date Title
JPS6344734A (en) Semiconductor device
JPH03138972A (en) Integrated circuit device
JPH04171843A (en) Gate array system lsi
JPH07106521A (en) Cell base designed semiconductor integrated circuit device
JPH02284448A (en) Semiconductor device
JP3452683B2 (en) Semiconductor integrated circuit device and power supply method thereof
JPH0247851A (en) Semiconductor integrated circuit device equipped with output buffer circuit
JPH01111342A (en) Package for integrated circuit
JPH04373143A (en) Semiconductor integrated circuit device
JPS6022327A (en) Semiconductor device
JPS60147126A (en) Semiconductor device
JPH05175334A (en) Semiconductor integrated circuit and layout method thereof
JPH0286131A (en) Semiconductor integrated device
JPH02306650A (en) Semiconductor device
JPH0360054A (en) Gate array
JPH0513582A (en) Power source wiring of semiconductor device
JPH09148545A (en) Semiconductor device
JPH0448779A (en) Semiconductor integrated circuit device
JPS6161448A (en) Integrated circuit device
JPH1012738A (en) Semiconductor integrated circuit device
JPH03232267A (en) Semiconductor integrated circuit device
JPH0485942A (en) Semiconductor integrated circuit
JPS59167036A (en) Semiconductor integrated circuit
JP2001116805A (en) Lsi package
JPH0318044A (en) Semiconductor integrated circuit device