JPH0128502B2 - - Google Patents

Info

Publication number
JPH0128502B2
JPH0128502B2 JP56162908A JP16290881A JPH0128502B2 JP H0128502 B2 JPH0128502 B2 JP H0128502B2 JP 56162908 A JP56162908 A JP 56162908A JP 16290881 A JP16290881 A JP 16290881A JP H0128502 B2 JPH0128502 B2 JP H0128502B2
Authority
JP
Japan
Prior art keywords
contact pad
members
alloy
gold
conductive paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56162908A
Other languages
English (en)
Other versions
JPS5799750A (en
Inventor
Furooren Joruju
Juruden Fuiritsupu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of JPS5799750A publication Critical patent/JPS5799750A/ja
Publication of JPH0128502B2 publication Critical patent/JPH0128502B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827Materials
    • H01L23/4828Conductive organic material or pastes, e.g. conductive adhesives, inks
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    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2924/14Integrated circuits
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    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Conductive Materials (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、金属化部である接触パツドをそれぞ
れが有する2個の部材間の多数の電気的接触を同
時に形成する方法に関するものである。
この方法によれば、前記部材の接触パツドは、
他方の前記部材の接触パツドに電気的に接続され
るようにされ、かつ、前記2個の部材が所定の位
置に互いに向き合わされるときに、前記部材の一
方によつて支持されている各接触パツドが他方の
前記部材の対応する接触パツドに対向して位置す
るようにされ、一定量の導電性ペーストを、前記
2個の部材のうちの少くとも一方の各接触パツド
に設けている。
本発明は、たとえば半導体素子を組立てる電子
工業に使用される。ハイブリツド回路の基板また
はくし状導体上での半導体素子の接続は、既知の
ように、半導体素子をそれらの接触パツドが互い
に対向するようにして基板またはくし状導体上に
設けることにより、および半導体素子の各接触パ
ツドとくし状導体の基板の対応する接触パツドと
の間に一定量の導電性ペースト、一般的には銀ま
たは金の粒子をまぜた(添加した)エポキシ樹脂
を設けた後に、たとえば加熱によつてペーストを
重合することによつて行うことができる。
このような方法は、英国特許第1525148号明細
書により知られている。この英国特許明細書は集
積回路の各接触パツド上に導電性グルー(glue)
の滴によつて、サブストレート上の集積回路に対
する接着方法について説明している。この英国特
許明細書は、さらに、アルミニウム・接触パツド
では、このパツド上の酸化アルミニウムを、少く
とも部分的に前もつて除去することを記載してい
る。接触パツドは、一般的にはアルミニウムであ
るため、この問題は非常に厄介である。一定の保
管期間の後に、除去された酸化アルミニウムが、
グルーがシールしないか、あるいはアルミニウム
が自己酸化されるか、あるいはこれら2つの可能
性が同時に生じることによつて、再び形成される
ことがわかつた。このことは、もちろん、接着の
中断および欠陥を含むものである。
この欠点を避けるためには、アルミニウム接触
パツドを、1以上の化学的、物理化学的または電
気化学的処理で処理して、導電性グルーと相れる
金属または合金がパツド上にデポジツトされるよ
うにする。しかし、この接着方法の利点は、この
方法が含む不良品(reject)および処理コストに
よつて大部分失われる。
本発明方法は、導電性ペーストとアルミニウム
パツドとの間に良好かつ耐久力のある品質の接触
を得ることを可能にする。この方法は、酸化アル
ミニウムを前もつて除去することを不必要とす
る。
本発明は、導電性ペーストの標準的な重合後
に、機械的な圧力と温度とを同時に供給すること
によつて、硬化ペースト中の導電性粒子と接触パ
ツドの表面との間に金属間接着を形成するという
考えに基いてなしたものである。重合導電性ペー
ストが加熱される温度は、初めに一定の軟化を生
じさせ、用いられる圧力は、熱圧縮の現象に類似
の現象によつて、電気的接続を形成する。接触パ
ツド上に酸化物皮膜があれば、この皮膜は貫通さ
れる。
本発明方法は、最初に、設けられた前記導電性
ペーストを重合させ、次に、重合した導電性ペー
ストを、前記2個の部材のうちの少くとも一方を
加熱しながら、部材の各接触パツドと他方の部材
の対応する接触パツドとの間で圧縮することを特
徴とするものである。
以下、本発明を図面に基いて詳細に説明する。
第1図は、非重合導電性ペーストの滴を設けた
基板の断面図である。
第2図は、導電性ペーストの加熱重合後の基板
の断面図である。
第3図は、基板上に設けられた半導体結晶の断
面図である。
これら3つの図は、本発明方法の3つの連続工
程をこの順序で示している。
説明する例は、ハイブリツド回路用の絶縁基板
上での半導体結晶の組立て、たとえば集積回路の
例である。この絶縁基板は、セラミツク材料であ
り、ホトエツチング処理によつて得られるたとえ
ば金の導体を有している。この金の導体は、既知
の方法によつて得られるたとえばニツケルおよび
ニツケルクロムの粘着層上に設けられている。第
1図は、2個の金メツキ金属化部2aおよび2b
を有する基板1を示す。これら金属化部から接触
パツドを形成する。
一定品質の導電性ペースト3aおよび3bを、
各導電性パツド2aおよび2b上に設ける。導電
性ペーストとして、“EPOTEK H44”の商標で
知られている、金粒子のまぜられたエポキシ樹脂
であるペーストを好適に用いることができる。た
とえば、銀粒子を有するエポキシ樹脂のような他
のペーストも適している。与えられる品質は、次
のように実験的に決定される。すなわち、硬化す
る前に、加熱重合の間にわずかに液体となつて流
れ出すペーストが、接触パツドと同じ寸法をほぼ
有する滴を形成する。前記ペーストの供給は、後
に分割される多数の基板を有するプレート上に、
シルクスクリーニング(silk―screening)によ
つて好適に行う。シルクスクリーニング・パター
ンは、金属箔によつて構成される。この金属箔
は、約20マイクロメータの厚さを有し、約80×80
マイクロメータのサイズを有する正方形孔が、ホ
トエツチングによつて設けられている。このプレ
ートを、ハイブリツド回路用の既知のシルクスク
リーニング・マシンのガーゼ(gauze)に粘着さ
せる。
第2図は、導電性ペーストを重合させた後の基
板1を示す。前述のペーストの場合、重合は、
150℃で1時間行う。前述したように、ペースト
3aおよび3bはわずかに流動して丸くなり、重
合後に硬化する。
第3図は、同じ基板1および金属化部2a,2
bを示すが、170℃±5℃に加熱されている。半
導体部材4の金属化部5a,5bは、重合ペース
ト滴3a,3b上に設けられている。次に圧力を
加えると、金属化部5aおよび5bは重合ペース
ト滴3aおよび3bに押圧される。この圧力は、
2〜3秒間保持され、接触パツドが100×100マイ
クロメータの寸法を有するときには1個の接触パ
ツドあたりほぼ100グラムに等しい。半導体部材
4を既知のように保持し、配置し、押圧するのに
役立つ真空ピペツト(図示せず)を、400℃±5
℃に加熱する。平坦な端部を有するピペツトを用
いて、この端部に接する半導体部材が破砕しない
ようにするのが好適である。導電性ペースト滴3
aおよび3bを押しつぶす。その結果、半導体部
材4と基板1との機械的接続および電気的接続
が、熱圧縮の現象に類似の現象によつて得られ
る。接触パツド5aおよび5bの金属が、酸化物
皮膜を有する場合には、熱圧縮に基づく接着の間
に酸化物皮膜は貫通される。
前述した方法は、主に、導電性ペースト3a,
3bを設け、重合したペーストを、部材の各接触
パツド2a,2bと他方の部材の対応する接触パ
ツド5a,5bとの間に、少くとも部材1,4の
一方を加熱している間に圧縮し、2つの部材1,
4がそれらの接触パツドで互いに配置される前
に、ペースト3a,3bの重合を行うことを特徴
としている。
本発明方法の変形実施例では、まだ重合されて
いない半導体ペースト3a,3bを設けた基板に
半導体部材4を設ける。次に、重合を行つて、半
導体部材1,4を最終的な相互位置に設ける。重
合は、たとえば、前述した導電性ペーストの場合
には、150℃1時間で行う。重合後、基板の温度
は170℃±5℃にまで上昇し、前述した加熱およ
び圧縮と同じ状況のもとで、加熱ピペツトを半導
体部材上に押圧する。
この実施例では、半導体部材4の接触パツド5
a,5bはアルミニウムであり、基板1の接触パ
ツド2a,2bは金であり、グルーは金がまぜら
れているが、本発明方法は、本発明の範囲内で他
の材料を有するアセンブリにおいて用いることが
できることは明らかである。たとえば、銅、ニツ
ケル、クロム、チタン、ゲルマニウム、シリコ
ン、モリブデン、コバルト、錫、カドミウム、
銀、プラチナ、パラジウムのような金属またはこ
れらの合金を用いることができる。
前述した状況のもとでは、μA741タイプの集積
回路の結晶は、100×100マイクロメータの7個の
接触パツドを有し、電気的接続は700〜800グラム
の圧力で得られ、このようにして製造されたアセ
ンブリは、150℃,1000時間の断続試験後も、そ
の品質を保持した。
【図面の簡単な説明】
第1図は、非重合導電性ペーストの滴を設けた
基板の断面図、第2図は、導電性ペーストの加熱
重合後の基板の断面図、第3図は、基板上に設け
られた半導体結晶の断面図である。 1……基板、2,5……接触パツド、3……導
電性ペースト、4……半導体部材。

Claims (1)

  1. 【特許請求の範囲】 1 金属化部である接触パツドをそれぞれが有す
    る2個の部材間の多数の電気的接続を同時に形成
    する方法であつて、前記部材の接触パツドは、他
    方の前記部材の接触パツドに電気的に接続される
    ようにされ、かつ、前記2個の部材が所定の位置
    に互いに向き合わされるときに、前記部材の一方
    によつて支持されている各接触パツドが他方の前
    記部材の対応する接触パツドに対向して位置する
    ようにされ、一定量の導電性ペーストを、前記2
    個の部材のうちの少なくとも一方の各接触パツド
    に設ける、2個の部材間に多数の電気的接続を同
    時に形成する方法において、最初に、設けられた
    前記導電性ペーストを重合させ、次に、重合した
    導電性ペーストを、前記2個の部材1,4のうち
    の少なくとも一方を加熱しながら、部材1の各接
    触パツド2a,2bと他方の部材4の対応する接
    触パツド5a,5bとの間で圧縮することを特徴
    とする2個の部材間に多数の電気的接続を同時に
    形成する方法。 2 特許請求の範囲第1項に記載の方法におい
    て、前記2個の部材の少なくとも一方の接触パツ
    ド2a,2b,5a,5bを、アルミニウム、
    銅、ニツケル、金、チタニウム、ゲルマニウム、
    シリコン、モリブデン、クロム、コバルト、錫、
    カドミウム、銀、プラチナ、パラジウム、銀―パ
    ラジウム合金、銀―プラチナ合金、コバルト―錫
    合金、コバルト―ニツケル合金、金―銅―カドミ
    ウム合金、金―銀合金、チタニウム―金合金、金
    ―バナジウム合金の群の中から選んだ金属とする
    ことを特徴とする方法。 3 特許請求の範囲第1項または第2項に記載の
    方法において、前記導電性ペースト3a,3bを
    銀粒子が添加されたエポキシ樹脂とすることを特
    徴とする方法。 4 特許請求の範囲第1項または第2項に記載の
    方法において、前記導電性ペースト3a,3bを
    金粒子が添加されたエポキシ樹脂とすることを特
    徴とする方法。
JP56162908A 1980-10-15 1981-10-14 Method of forming electric connection Granted JPS5799750A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8022083A FR2492164B1 (fr) 1980-10-15 1980-10-15 Procede de realisation simultanee de liaisons electriques multiples, notamment pour le raccordement electrique d'une micro-plaquette de semiconducteurs

Publications (2)

Publication Number Publication Date
JPS5799750A JPS5799750A (en) 1982-06-21
JPH0128502B2 true JPH0128502B2 (ja) 1989-06-02

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ID=9246931

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Application Number Title Priority Date Filing Date
JP56162908A Granted JPS5799750A (en) 1980-10-15 1981-10-14 Method of forming electric connection

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Country Link
US (1) US4442966A (ja)
JP (1) JPS5799750A (ja)
DE (1) DE3140348A1 (ja)
FR (1) FR2492164B1 (ja)
GB (1) GB2090071B (ja)
IE (1) IE52529B1 (ja)

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Also Published As

Publication number Publication date
FR2492164A1 (fr) 1982-04-16
US4442966A (en) 1984-04-17
GB2090071A (en) 1982-06-30
FR2492164B1 (fr) 1987-01-23
JPS5799750A (en) 1982-06-21
DE3140348A1 (de) 1982-08-26
IE52529B1 (en) 1987-12-09
GB2090071B (en) 1984-05-23
IE812380L (en) 1982-04-15

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