JPH01170028A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01170028A JPH01170028A JP62327083A JP32708387A JPH01170028A JP H01170028 A JPH01170028 A JP H01170028A JP 62327083 A JP62327083 A JP 62327083A JP 32708387 A JP32708387 A JP 32708387A JP H01170028 A JPH01170028 A JP H01170028A
- Authority
- JP
- Japan
- Prior art keywords
- film
- film carrier
- wiring board
- printed wiring
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000008188 pellet Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 abstract description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000009719 polyimide resin Substances 0.000 abstract description 2
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 239000000969 carrier Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 241001071864 Lethrinus laticaudis Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、フィルムキャリヤ方式による半導体装置の高
密度実装に適用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to high-density packaging of semiconductor devices using a film carrier method.
フィルムキャリヤ方式により組み立てられる半導体装置
（以下、単にフィルムキャリヤという）の高密度実装技
術については、例えば、本出願人による特開昭！”４−
８７１７３号公報記載の発明があり、一対の半導体ペレ
ット（以下、ペレットという）をそれらのバンプ同士が
向き合うように重ね合わせてパッケージに封止した装置
構造が開示されている。Regarding high-density packaging technology for semiconductor devices assembled using a film carrier method (hereinafter simply referred to as a film carrier), for example, the present applicant's Japanese Patent Application Laid-open Sho! "4-
There is an invention described in Japanese Patent No. 87173, which discloses a device structure in which a pair of semiconductor pellets (hereinafter referred to as pellets) are stacked so that their bumps face each other and sealed in a package.
また、フィルムキャリアをモジニール基板などの印刷配
線板上に高密度に実装する技術として、従来より、両面
実装方式、あるいは、複数個のフィルムキャリアを重ね
て実装する、いわゆるビギー・バック（ｐｉｇｇｙ−ｂ
ａｃｋ）方式などが知られている。In addition, as a technology for high-density mounting of film carriers on a printed wiring board such as a modular board, conventional methods have been used, such as the double-sided mounting method or the so-called piggy-back method, in which multiple film carriers are mounted on top of each other.
ack) method is known.
本発明者は、上記した両面実装方式やピギー・パック方
式など、従来のフィルムキャリアの実装方式には、下記
のような問題点のあることを見出した。The present inventor has discovered that conventional film carrier mounting methods, such as the above-mentioned double-sided mounting method and piggy pack method, have the following problems.
まず、両面実装方式の場合において、同一の回路機能を
有するペレットがボンディングされた二個のフィルムキ
ャリアを印刷配線板の両面に対向配置させると、ペレッ
トの入出力ピン配置が互いに逆向きとなるため、メモリ
素子などのように、それらの入出力ピン同士を接続して
使用する場合には、印刷配線板の表面や内層の配線を長
くしなければならないため、印刷配線板の実装密度が低
下してしまうという問題がある。First, in the case of double-sided mounting, if two film carriers to which pellets with the same circuit function are bonded are placed facing each other on both sides of a printed wiring board, the input and output pins of the pellets will be arranged in opposite directions. , memory devices, etc., when the input and output pins are connected to each other, the wiring on the surface and inner layer of the printed wiring board must be made longer, which reduces the packaging density of the printed wiring board. There is a problem with this.
一方、ビギー・バック方式の場合には、各ペレットの入
出力ビン配置が重なり合うので上記のような問題は生じ
ないが、反面、印刷配線板に実装する際、上段のフィル
ムキャリアと下段のフィルムキャリアとでそれらのアウ
タリードの長さを変えなければならないため、アウタリ
ードの切断工程やフォーミング工程が煩雑になり、実装
工程のスループットが低下してしまうという問題がある
。On the other hand, in the case of the biggie back method, the input and output bins of each pellet overlap, so the above problem does not occur. Since the lengths of the outer leads must be changed depending on the length of the outer leads, the process of cutting and forming the outer leads becomes complicated, resulting in a problem that the throughput of the mounting process is reduced.
本発明は、上記した問題点に着目してなされたものであ
り、その目的は、フィルムキャリアを高密度に実装する
ことのできる技術を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that allows film carriers to be mounted at high density.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、フィルムの表面に形成されたアウタリードの
引き出し方向をインナリードの配列方向に対して所定の
角度をなすように配向させたフィルムキャリヤである。That is, it is a film carrier in which the direction in which the outer leads formed on the surface of the film are drawn out is oriented at a predetermined angle with respect to the direction in which the inner leads are arranged.
上記した手段によれば、アウタリードをフィルム表面の
所望する方向に引き出すことができるため、印刷配線板
の配線が簡略化され、フィルムキャリヤを高密度に実装
できるようになる。According to the above-mentioned means, since the outer lead can be pulled out in a desired direction on the film surface, the wiring of the printed wiring board can be simplified and the film carrier can be mounted with high density.
第１図は本発明の一実施例である半導体装置の要部平面
図、第２図および第３図は印刷配線板に実装されたこの
半導体装置の要部拡大断面図である。FIG. 1 is a plan view of the main part of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are enlarged sectional views of the main part of this semiconductor device mounted on a printed wiring board.
本実施例の半導体装置は、表面にリードパターン１が形
成されたフィルム２と、上記リードパターン１のインナ
リード１ａにボンディングされたペレット３とからなる
フィルムキャリヤ４ａである。The semiconductor device of this embodiment is a film carrier 4a comprising a film 2 having a lead pattern 1 formed on its surface, and a pellet 3 bonded to the inner lead 1a of the lead pattern 1.
図示しない集積回路が形成されたペレット３の上面には
、その左右両端部に沿って多数の電極５が形成され、各
電極５には、バンプ６が取り付けられている。A large number of electrodes 5 are formed along both left and right ends of the upper surface of the pellet 3 on which an integrated circuit (not shown) is formed, and a bump 6 is attached to each electrode 5.
ポリイミド樹脂などからなるフィルム２の表面に形成さ
れたリードパターン１は、例えば、表面にスズ（Ｓｎ）
などのメツキが施された銅（Ｃｕ）からなり、第１０に
示すように、そのアウタリード１ｂがインナリード１ａ
の配列方向に対して１８０度の角度をなすように引き出
されている。The lead pattern 1 formed on the surface of the film 2 made of polyimide resin or the like is made of, for example, tin (Sn) on the surface.
As shown in No. 10, the outer lead 1b is made of copper (Cu) plated with the inner lead 1a.
are drawn out at an angle of 180 degrees with respect to the arrangement direction.
上記フィルムキャリヤ４ａは、通常のフィルムキャリヤ
と同様のプロセスで作成することができる。The film carrier 4a can be produced by the same process as a normal film carrier.
例えば、パンチングにより所定個所を穴開けしてスプロ
ケットホール７およびスリット８ａ、８ｂ、ｇｃを形成
したフィルム２の表面に銅箔を接着し、エツチングによ
り上記リードパターンｌを形成した後、その表面にメツ
キを施す。For example, copper foil is bonded to the surface of the film 2 on which sprocket holes 7 and slits 8a, 8b, and gc are formed by punching holes at predetermined locations, and after the lead pattern l is formed by etching, the surface is plated. administer.
一方、所定の集積回路を形成した半導体ウェハの各電極
５に金（Ａｕ）などからなるバンブ６を取り付けた後、
この半導体ウェハをグイシングしてペレット３を作成す
る。On the other hand, after attaching bumps 6 made of gold (Au) or the like to each electrode 5 of a semiconductor wafer on which a predetermined integrated circuit has been formed,
This semiconductor wafer is subjected to guising to create pellets 3.
次いで、ボンディングツールを用いてインナリード１ａ
にペレット３ををボンディングすることにより、アウタ
リード１ｂの引き出し方向がインナリード１ａの配列方
向に対して１８０度の角度をなすように配向された、す
なわち、アウタリード１ｂの配列がペレット３の電極５
の配列と逆向きとなったフィルムキャリヤ４ａが得られ
る。Next, the inner lead 1a is bonded using a bonding tool.
By bonding the pellet 3 to the electrode 5 of the pellet 3, the outer lead 1b is oriented so that the direction in which the outer lead 1b is pulled out forms an angle of 180 degrees with respect to the arrangement direction of the inner lead 1a.
A film carrier 4a is obtained in which the orientation is opposite to that of the film carrier 4a.
その後、フィルムキャリヤ４ａのペレット３の周囲をエ
ポキシ樹脂（図示せず）などで封止してフィルムキャリ
ヤ４ａを所定の専用リールに巻き取り、実装工程に搬送
する。Thereafter, the periphery of the pellet 3 on the film carrier 4a is sealed with epoxy resin (not shown) or the like, and the film carrier 4a is wound onto a predetermined dedicated reel and transported to a mounting process.
以下、上記フィルムキャリヤ４ａの実装方法を説明する
。A method for mounting the film carrier 4a will be described below.
第２図は、本実施例のフィルムキャリヤ４ａと従来のフ
ィルムキャリヤ４ｂとを印刷配線板９を挟んで両面実装
した構造を示し、両フィルムキャリヤ４ａ、４ｂのイン
ナリードｌａ、ｌａにボンディングされたベレット３，
３は互いに同一の回路機能を有するものである。FIG. 2 shows a structure in which the film carrier 4a of this embodiment and the conventional film carrier 4b are mounted on both sides with a printed wiring board 9 in between, and the inner leads la and la of both film carriers 4a and 4b are bonded. Beret 3,
3 have the same circuit function.
印刷配線板９の下面に半田付けされた従来のフィルムキ
ャリヤ４ｂは、アウタリード１ｂの引き出し方向がイン
ナリード１ａの配列と平行になっており、他方、印刷配
線板９の上面に半田付けされた本実施例のフィルムキャ
リヤ４ａは、前記したように、アウタリードｌｂの引き
出し方向がインナリード１ａの配列方向に対して１８０
度の角度に配向されたものである。In the conventional film carrier 4b soldered to the lower surface of the printed wiring board 9, the direction in which the outer leads 1b are pulled out is parallel to the arrangement of the inner leads 1a, and the film carrier 4b soldered to the upper surface of the printed wiring board 9 is As described above, in the film carrier 4a of the embodiment, the direction in which the outer leads lb are pulled out is 180 degrees with respect to the arrangement direction of the inner leads 1a.
It is oriented at a degree angle.
従って、第２図に示す両面実装構造においては、上記両
ペレット３．３の入出力ピン配置が印刷配線板９を挟ん
で互いに逆向きとなるが、上記アウタリード１ｂ、１ｂ
の配列が重なり合うため、印刷配線板９にスルーホール
１０を形成して対向するアウタリードｌｂ、ｌｂ同士を
接続するだけで、入出力ビン同士の接続が可能となる。Therefore, in the double-sided mounting structure shown in FIG.
Since the arrays overlap, the input/output bins can be connected to each other by simply forming through holes 10 in the printed wiring board 9 and connecting the opposing outer leads lb, lb.
また、本実施例のフィルムキャリヤ４ａと従来のフィル
ムキャリヤ４ｂとをそれらのバンプ６゜６の形成面同士
が向き合うように重ね合わせると、第３図に示すような
、ピギー・バック方式と両面実装方式とを組み合わせた
実装構造が得られる。Furthermore, when the film carrier 4a of this embodiment and the conventional film carrier 4b are placed one on top of the other so that the surfaces on which the bumps 6°6 are formed face each other, a piggyback method and a double-sided mounting method can be realized as shown in FIG. A mounting structure that combines these methods can be obtained.
この場合も、上段のフィルムキャリヤ４ａのアウタリー
ド１ｂと下段のフィルムキャリヤ４ｂのアウタリード！
ｂとを接続するだけで、両ペレット３．３の入出力ピン
同士の接続が可能となる。In this case as well, the outer lead 1b of the upper film carrier 4a and the outer lead of the lower film carrier 4b!
By simply connecting b, the input and output pins of both pellets 3.3 can be connected to each other.
また、上記実装構造においては、各フィルムキャリヤ４
ａ、４ａ、４ｂ、４ｂのアウタリード１ｂがすべて同一
形状でフォーミングできるため、アウタリードの切断工
程やフォーミング工程も簡略化される。In addition, in the above mounting structure, each film carrier 4
Since the outer leads 1b of a, 4a, 4b, and 4b can all be formed into the same shape, the cutting process and forming process of the outer leads are also simplified.
なおこの場合、第３図に示すように、印刷配線板９の上
下面に凹ｍ５１１．１１を設けてそこに下段のフィルム
キャリヤ４ａ、４ｂを配置させることにより、上下方向
の厚みの少ない実装構造が得られる。In this case, as shown in FIG. 3, by providing recesses m511.11 on the upper and lower surfaces of the printed wiring board 9 and arranging the lower film carriers 4a and 4b therein, a mounting structure with less thickness in the vertical direction can be achieved. is obtained.
このように、本実施例によれば、次の効果を得ることが
できる。As described above, according to this embodiment, the following effects can be obtained.
（１）、アウタリードｌｂの引き出し方向をインナリー
ド１ａの配列方向に対して１８０度の角度をなすように
配向させたフィルムキャリヤ４ａと、アウタリード１ｂ
の引き出し方向がインナリード１ａの配列と平行になっ
た従来のフィルムキャリヤ４ｂとを、それらのバンブ６
．６の形成面同士が向き合うように対向配置すると、両
フィルムキャリヤ４ａ、４ｂのベレット３．３の各人出
力ピンに接続されたアウタリード１ｂ、Ｉｂの配列が一
致する。(1) A film carrier 4a oriented such that the direction in which the outer leads lb are pulled out forms an angle of 180 degrees with respect to the arrangement direction of the inner leads 1a, and the outer leads 1b.
A conventional film carrier 4b whose drawing direction is parallel to the arrangement of the inner leads 1a, and the bumps 6
．． When the outer leads 1b and Ib connected to the respective output pins of the bullets 3.3 of both film carriers 4a and 4b are arranged to face each other so that the formed surfaces of the film carriers 4a and 4b face each other, the outer leads 1b and Ib are arranged in the same manner.
これにより、フィルムキャリヤ４ａ、４ｂを両面実装方
式で印刷配線板９に実装する場合には、スルーホール１
０を介して対向するアウタリード１ｂ、１ｂ同士を接続
するだけで人出力ピン同士の接続が可能となり、これに
より、印刷配線板９の配線が簡素化され、その実装密度
が向上する。As a result, when mounting the film carriers 4a and 4b on the printed wiring board 9 using a double-sided mounting method, the through holes 1
The human output pins can be connected to each other by simply connecting the outer leads 1b, 1b facing each other via 0, thereby simplifying the wiring on the printed wiring board 9 and improving its packaging density.
また、フィルムキャリヤ４ａ、４ｂをピギー・バック方
式で印刷配線板９に実装する場合には、上下段のフィル
ムキャリヤ４ａ、４ｂ’のアウタリードＩｂ、１ｂを同
一形状とすることができるので、その切断工程やフォー
ミング工程が簡略化され、実装工程のスルーブツトが向
上する。Furthermore, when mounting the film carriers 4a, 4b on the printed wiring board 9 in a piggyback manner, the outer leads Ib, 1b of the upper and lower film carriers 4a, 4b' can be made to have the same shape, so that the outer leads Ib, 1b can be cut. The process and forming process are simplified, and the throughput of the mounting process is improved.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
例えば、第４図に示すように、アウタリード１ｂの引き
出し方向をインナリード１ａの配列方向に対して９０度
の角度をなすように配向させたフィルムキャリヤ４ｃと
するなど、アウタリード１ｂの引き出し方向は、印刷配
線板への実装方式などに応じて所望する角度だけ配向さ
せることができ、これにより、印刷配線板の配線が簡略
化され、一定のスペース内により多くのフィルムキャリ
ヤを実装することが可能となる。For example, as shown in FIG. 4, the direction in which the outer leads 1b are drawn out may be set to a film carrier 4c that is oriented so that the direction in which the outer leads 1b are drawn out forms an angle of 90 degrees to the direction in which the inner leads 1a are arranged. The film carrier can be oriented at a desired angle depending on the mounting method on the printed wiring board, etc. This simplifies the wiring on the printed wiring board and allows more film carriers to be mounted in a given space. Become.
本願にふいて開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、フィルムキャリヤのフィルム表面に形成され
たアウタリードをインナリードの配列方向に対して所定
の角度をなすように配向させて所望する方向に引き出す
ことにより、印刷配線板の配線が簡略化され、その実装
密度が向上する。That is, by orienting the outer leads formed on the film surface of the film carrier at a predetermined angle with respect to the arrangement direction of the inner leads and pulling them out in a desired direction, the wiring of the printed wiring board can be simplified. Improves packaging density.
第１図は本発明の一実施例である半導体装置の要部平面
図、
第２図および第３図は印刷配線板に実装されたこの半導
体装置の要部拡大断面図、
第４図は本発明の他の実施例である半導体装置の要部平
面図である。
１・・・リードパターン、１ａ・・・インナリード、Ｉ
ｂ・・・アウタリード、２・・・フィルム、３・・・半
導体ベレット、４ａ、４ｂ、４ｃ・・・フィルムキャリ
ヤ（半導体装置）、５・・・電極、６・・・バンプ、７
・・・スプロケットホール、８ａ、８ｂ、８ｃ・・・ス
リット、９・・・印刷配線板、１０・・・スルーホール
、１１・・・凹部。FIG. 1 is a plan view of the main parts of a semiconductor device which is an embodiment of the present invention, FIGS. 2 and 3 are enlarged cross-sectional views of the main parts of this semiconductor device mounted on a printed wiring board, and FIG. FIG. 7 is a plan view of a main part of a semiconductor device according to another embodiment of the invention. 1... Lead pattern, 1a... Inner lead, I
b... Outer lead, 2... Film, 3... Semiconductor pellet, 4a, 4b, 4c... Film carrier (semiconductor device), 5... Electrode, 6... Bump, 7
... Sprocket hole, 8a, 8b, 8c... Slit, 9... Printed wiring board, 10... Through hole, 11... Recess.
Claims (1)
ナリードに半導体ペレットをボンディングしてなる半導
体装置であって、前記リードパターンのアウタリードの
引き出し方向を前記インナリードの配列方向に対して所
定の角度をなすように配向させたことを特徴とする半導
体装置。 ２、アウタリードの引き出し方向をインナリードの配列
方向に対して１８０度の角度をなすように配向させたこ
とを特徴とする特許請求範囲第１項記載の半導体装置。 ３、アウタリードの引き出し方向をインナリードの配列
方向に対して９０度の角度をなすように配向させたこと
を特徴とする特許請求範囲第１項記載の半導体装置。[Claims] 1. A semiconductor device in which semiconductor pellets are bonded to inner leads of a lead pattern formed on the surface of a film, wherein the outer leads of the lead pattern are drawn out in a direction in which the inner leads are arranged. 1. A semiconductor device characterized in that the semiconductor device is oriented at a predetermined angle with respect to the semiconductor device. 2. The semiconductor device according to claim 1, wherein the outer leads are drawn out in a direction that is oriented at an angle of 180 degrees with respect to the arrangement direction of the inner leads. 3. The semiconductor device according to claim 1, wherein the outer leads are drawn out in a direction that makes an angle of 90 degrees with respect to the arrangement direction of the inner leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62327083A JPH0828393B2 (en) | 1987-12-25 | 1987-12-25 | Electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62327083A JPH0828393B2 (en) | 1987-12-25 | 1987-12-25 | Electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01170028A true JPH01170028A (en) | 1989-07-05 |
| JPH0828393B2 JPH0828393B2 (en) | 1996-03-21 |
Family
ID=18195097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62327083A Expired - Lifetime JPH0828393B2 (en) | 1987-12-25 | 1987-12-25 | Electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828393B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5490041A (en) * | 1993-11-15 | 1996-02-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit module and a semiconductor integrated circuit device stacking the same |
| US6424030B2 (en) * | 1987-06-24 | 2002-07-23 | Hitachi, Ltd. | Semiconductor memory module having double-sided stacked memory chip layout |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710956A (en) * | 1980-06-24 | 1982-01-20 | Ricoh Co Ltd | Tape carrier |
| JPS58103160A (en) * | 1981-12-16 | 1983-06-20 | Ricoh Co Ltd | Remounting of tape carrier |
| JPS5927560A (en) * | 1982-08-04 | 1984-02-14 | Ricoh Co Ltd | Mounting method for ic chip |
-
1987
- 1987-12-25 JP JP62327083A patent/JPH0828393B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710956A (en) * | 1980-06-24 | 1982-01-20 | Ricoh Co Ltd | Tape carrier |
| JPS58103160A (en) * | 1981-12-16 | 1983-06-20 | Ricoh Co Ltd | Remounting of tape carrier |
| JPS5927560A (en) * | 1982-08-04 | 1984-02-14 | Ricoh Co Ltd | Mounting method for ic chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6424030B2 (en) * | 1987-06-24 | 2002-07-23 | Hitachi, Ltd. | Semiconductor memory module having double-sided stacked memory chip layout |
| US5490041A (en) * | 1993-11-15 | 1996-02-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit module and a semiconductor integrated circuit device stacking the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0828393B2 (en) | 1996-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4996583A (en) | Stack type semiconductor package | |
| US6504244B2 (en) | Semiconductor device and semiconductor module using the same | |
| US7049687B2 (en) | Tape carrier package having stacked semiconductor elements, and short and long leads | |
| US6300685B1 (en) | Semiconductor package | |
| US6791166B1 (en) | Stackable lead frame package using exposed internal lead traces | |
| US20060194369A1 (en) | Carrier for substrate film | |
| KR100618542B1 (en) | Method for manufacturing stack package | |
| JPH08264712A (en) | Semiconductor device | |
| US6103548A (en) | Semiconductor device and method of manufacture | |
| JPH01170028A (en) | Semiconductor device | |
| US5118556A (en) | Film material for film carrier manufacture and a method for manufacturing film carrier | |
| JPH01137660A (en) | Semiconductor device | |
| JP2513724B2 (en) | Carrier tape for semiconductor device | |
| JP3630713B2 (en) | Surface mounting package and package mounting apparatus | |
| KR100675729B1 (en) | Stack package using flexible substrate | |
| JPH0719165Y2 (en) | Multi-chip structure | |
| JPH04162656A (en) | Semiconductor integrated circuit device and packaging structure thereof | |
| JPH02290048A (en) | Laminated semiconductor mounted body | |
| JPH0232547A (en) | Semiconductor packaging device | |
| JP2806816B2 (en) | Bonding apparatus and bonding method using the same | |
| KR100779344B1 (en) | Semiconductor package | |
| JP3434807B2 (en) | Tape carrier package and manufacturing method thereof | |
| KR100633884B1 (en) | Manufacturing method of semiconductor package | |
| JPH10189813A (en) | Semiconductor device, laminated-type semiconductor device and their mounting structure | |
| JPS63164226A (en) | Manufacture of tape carrier element |