JPH0232547A - Semiconductor packaging device - Google Patents
Semiconductor packaging deviceInfo
- Publication number
- JPH0232547A JPH0232547A JP18173488A JP18173488A JPH0232547A JP H0232547 A JPH0232547 A JP H0232547A JP 18173488 A JP18173488 A JP 18173488A JP 18173488 A JP18173488 A JP 18173488A JP H0232547 A JPH0232547 A JP H0232547A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- lead
- lsi
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004806 packaging method and process Methods 0.000 title abstract description 3
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 201000004997 drug-induced lupus erythematosus Diseases 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＬＳＩチップによる半導体装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device using an LSI chip.
（従来の技術） 近年、ＬＳＩの発展に伴い、全ての機器が小型。(Conventional technology) In recent years, with the development of LSI, all devices have become smaller.
軽量、薄型化の傾向にある。更にその小型、軽量。There is a trend toward lighter weight and thinner products. Furthermore, it is small and lightweight.
薄型化を進めるためには、ＬＳＩを如何に高密度に回路
基板に搭載するかが重要な要素となる。In order to promote thinning, an important factor is how densely LSIs can be mounted on circuit boards.
従来、高密度化を計るため、ＬＳＩのプリント配線板へ
の搭載方法は、リード端子を有するフラットパッケージ
、ＤＩＬ、ＳＯＰ等のパッケージを用い、このパッケー
ジを平面的に配置するものであった。Conventionally, in order to achieve high density, the method for mounting LSIs on printed wiring boards has been to use packages such as flat packages, DILs, and SOPs having lead terminals, and to arrange these packages in a two-dimensional manner.
（発明が解決しようとする課題）
上記のように、従来の方法では、ＬＳＩチップを一旦パ
ッケージに入れ、このパッケージを平面的に配設するも
のであるから、実装面積が大きく、機器のこれ以上の小
型化は回連であった。(Problems to be Solved by the Invention) As mentioned above, in the conventional method, the LSI chip is once placed in a package and this package is arranged on a flat surface, so the mounting area is large and the device The downsizing was repeated.
本発明は、従来よりも格段に優れた実装密度を得られる
半導体装置を提供するものである。The present invention provides a semiconductor device that can achieve a packaging density that is much higher than that of the conventional semiconductor device.
（課題を解決するための手段）
そこで本発明は、リードを有するＬＳＩチップを複数個
積層し、これら各ＬＳＩチップの各リードをプリント配
線板に接続したものである。(Means for Solving the Problems) Accordingly, the present invention is such that a plurality of LSI chips having leads are stacked, and each lead of each of these LSI chips is connected to a printed wiring board.
（作 用）
複数個のＬＳＩチップをプリント配線板上に積層し、各
リードをプリント配線板に接続するようにしたので、高
密度に、しかも比較的薄い厚さにＬＳＩチップを実装で
きる。(Function) Since a plurality of LSI chips are stacked on a printed wiring board and each lead is connected to the printed wiring board, the LSI chips can be mounted with high density and relatively thin thickness.
（実施例）
第１図は本発明に用いる一例のＬＳＩチップのリード取
付状態を示し、ＬＳＩチップ１の電極とリード３とが金
属突起２において接合される。リード３は、同図中の所
定の破線領域５より切断される。(Embodiment) FIG. 1 shows a lead attachment state of an example of an LSI chip used in the present invention, in which electrodes of an LSI chip 1 and leads 3 are joined at metal protrusions 2. As shown in FIG. The lead 3 is cut from a predetermined broken line area 5 in the figure.
第２図は本発明の一実施例を示し、プリント配線板６上
にＬＳＩチップ１を複数個（この例では３個）積層し、
各ＬＳＩチップ１のリード３をそれぞれ所要形状に折曲
して、プリント配線板６の電極７に接続する。リード３
はフィルムキャリア方式で構成されるため、可撓性を有
し容易に所要形状に成型加工ができるものであり、リー
ド３がＬＳＩチップ１から水平方向に導出されていても
。FIG. 2 shows an embodiment of the present invention, in which a plurality of LSI chips 1 (three in this example) are stacked on a printed wiring board 6,
The leads 3 of each LSI chip 1 are bent into a desired shape and connected to electrodes 7 of a printed wiring board 6. lead 3
Since it is constructed using a film carrier method, it has flexibility and can be easily molded into a desired shape, even if the leads 3 are led out from the LSI chip 1 in a horizontal direction.
チップ１をＭｆｆしてから加熱治具のパルスツール等で
リード３を押さえると、リード３は容易に変形し、更に
加熱すると、プ・リント配線板６の電極７に接合できる
。If the leads 3 are pressed with a pulse tool of a heating jig after Mffing the chip 1, the leads 3 are easily deformed and can be bonded to the electrodes 7 of the printed wiring board 6 by further heating.
第３図は他の実施例を示し、積層されたチップ１と１′
とは、互いのリード３，３′が重ならないよう平面的に
斜方向にずらされており、リード３゜３′はそれぞれプ
リント配線板の異なった電極７゜７′に接続される。す
なわち、各ＬＳＩチップ１゜１′のリードを個々にプリ
ント配線板上の各電極に接続できる。FIG. 3 shows another embodiment in which chips 1 and 1' are stacked together.
The leads 3, 3' are shifted obliquely in a plane so that they do not overlap each other, and the leads 3, 3' are respectively connected to different electrodes 7, 7' of the printed wiring board. That is, the leads of each LSI chip 1.degree. 1' can be individually connected to each electrode on the printed wiring board.
第４図は更に他の実施例を示し、この例では、積層した
各層のＬＳＩチップ１のリード３間に、第５図で斜視図
が示されるスペーサ８を入れ積層したものである。この
スペーサ８はＬＳＩチップ１の外周を囲み、その肉厚は
ＬＳＩチップ１の肉厚とほぼ同じである。また、このス
ペーサ８にはり−ド３が置かれる位置に導電層９が設け
られ、上下方向のリード、もしくは隣同士のリードが接
続され、この導電層９を介して各リードはプリント配線
板６の各電極７へ接続される。FIG. 4 shows yet another embodiment, in which a spacer 8, whose perspective view is shown in FIG. 5, is inserted between the leads 3 of the LSI chips 1 in each stacked layer. This spacer 8 surrounds the outer periphery of the LSI chip 1, and its thickness is approximately the same as that of the LSI chip 1. Further, a conductive layer 9 is provided on this spacer 8 at a position where the solder board 3 is placed, and the leads in the vertical direction or adjacent leads are connected to each other, and each lead is connected to the printed wiring board 6 through the conductive layer 9. is connected to each electrode 7 of.
（発明の効果）
以−ヒのように１本発明によれば、ＬＳＩチップをパッ
ケージに入れることなくプリント配線板に積層して実装
するものであるから、比較的薄くして従来装置より格段
に高密度に実装できる。従って、これを使用する機器を
小型、薄型、軽量化し得る。(Effects of the Invention) As described below, according to the present invention, the LSI chip is mounted by laminating it on a printed wiring board without putting it in a package, so it can be made relatively thinner and much more efficient than the conventional device. Can be mounted in high density. Therefore, equipment using this can be made smaller, thinner, and lighter.
第１５図は本発明に用いるＬＳＩチップのリード取付状
態を示す平面図、第２図は本発明の一実施例の縦断面図
、第３図は他の実施例の平面図、第４図は更に他の実施
例の縦断面図、第５図はスペーサの斜視図である。
１．１′・・・ＬＳＩチップ、 ３，３′・・・リー
ド、 ６・・・プリント配線板、 ８・・・スペーサ
、 ９・・・導電層。
特許出願人 松下電器産業株式会社
第１図
１ ・・・ ＬＳＩ＋ッフ
３・・・ リーＹ
第 ２
図
・・・ ＬＳＩ＋ッフ。
３・・・
ノード
６ °°°フ゛°ルト配ｈト板
竿
図FIG. 15 is a plan view showing the lead attachment state of an LSI chip used in the present invention, FIG. 2 is a longitudinal sectional view of one embodiment of the present invention, FIG. 3 is a plan view of another embodiment, and FIG. FIG. 5 is a longitudinal cross-sectional view of still another embodiment, and FIG. 5 is a perspective view of a spacer. 1.1'... LSI chip, 3,3'... Lead, 6... Printed wiring board, 8... Spacer, 9... Conductive layer. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 1... LSI + ff 3... Lee Y Figure 2... LSI + ff. 3... Node 6 °°° field wiring board diagram
Claims (3)
れらＬＳＩチップの各リードをプリント配線板に接続し
たことを特徴とする半導体実装装置。(1) A semiconductor mounting device characterized in that a plurality of LSI chips having leads are stacked and each lead of these LSI chips is connected to a printed wiring board.
面的にずらせて積層したことを特徴とする請求項（１）
記載の半導体実装装置。(2) Claim (1) characterized in that each LSI chip is stacked with the leads shifted in a plane so that the leads do not overlap with each other.
The semiconductor mounting device described.
ード間にそれぞれ配置積層されたスペーサに設けた導電
層を介してプリント配線板に接続したことを特徴とする
請求項（１）記載の半導体実装装置。(3) The semiconductor according to claim (1), wherein the leads of each LSI chip are connected to the printed wiring board via a conductive layer provided on a spacer arranged and laminated between the leads of each LSI chip. Mounting equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63181734A JPH0787236B2 (en) | 1988-07-22 | 1988-07-22 | Semiconductor mounting equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63181734A JPH0787236B2 (en) | 1988-07-22 | 1988-07-22 | Semiconductor mounting equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0232547A true JPH0232547A (en) | 1990-02-02 |
| JPH0787236B2 JPH0787236B2 (en) | 1995-09-20 |
Family
ID=16105953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63181734A Expired - Fee Related JPH0787236B2 (en) | 1988-07-22 | 1988-07-22 | Semiconductor mounting equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0787236B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06275775A (en) * | 1993-03-17 | 1994-09-30 | Nec Corp | Semiconductor device |
| US5394010A (en) * | 1991-03-13 | 1995-02-28 | Kabushiki Kaisha Toshiba | Semiconductor assembly having laminated semiconductor devices |
| US5701031A (en) * | 1990-04-26 | 1997-12-23 | Hitachi, Ltd. | Sealed stacked arrangement of semiconductor devices |
| US7834440B2 (en) * | 2008-09-29 | 2010-11-16 | Hitachi, Ltd. | Semiconductor device with stacked memory and processor LSIs |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4845563U (en) * | 1971-09-27 | 1973-06-14 | ||
| JPS56137665A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
| JPS60151136U (en) * | 1984-03-16 | 1985-10-07 | 三洋電機株式会社 | Semiconductor memory mounting structure |
| JPS62122359U (en) * | 1986-01-24 | 1987-08-03 | ||
| JPS6361150U (en) * | 1986-10-13 | 1988-04-22 |
-
1988
- 1988-07-22 JP JP63181734A patent/JPH0787236B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4845563U (en) * | 1971-09-27 | 1973-06-14 | ||
| JPS56137665A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
| JPS60151136U (en) * | 1984-03-16 | 1985-10-07 | 三洋電機株式会社 | Semiconductor memory mounting structure |
| JPS62122359U (en) * | 1986-01-24 | 1987-08-03 | ||
| JPS6361150U (en) * | 1986-10-13 | 1988-04-22 |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701031A (en) * | 1990-04-26 | 1997-12-23 | Hitachi, Ltd. | Sealed stacked arrangement of semiconductor devices |
| USRE37539E1 (en) * | 1990-04-26 | 2002-02-05 | Hitachi, Ltd. | Sealed stacked arrangement of semiconductor devices |
| US5394010A (en) * | 1991-03-13 | 1995-02-28 | Kabushiki Kaisha Toshiba | Semiconductor assembly having laminated semiconductor devices |
| JPH06275775A (en) * | 1993-03-17 | 1994-09-30 | Nec Corp | Semiconductor device |
| JP2842753B2 (en) * | 1993-03-17 | 1999-01-06 | 日本電気株式会社 | Semiconductor device |
| US7834440B2 (en) * | 2008-09-29 | 2010-11-16 | Hitachi, Ltd. | Semiconductor device with stacked memory and processor LSIs |
| US7977781B2 (en) | 2008-09-29 | 2011-07-12 | Hitachi, Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0787236B2 (en) | 1995-09-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |