JPH04162656A - Semiconductor integrated circuit device and packaging structure thereof - Google Patents
Semiconductor integrated circuit device and packaging structure thereofInfo
- Publication number
- JPH04162656A JPH04162656A JP28704890A JP28704890A JPH04162656A JP H04162656 A JPH04162656 A JP H04162656A JP 28704890 A JP28704890 A JP 28704890A JP 28704890 A JP28704890 A JP 28704890A JP H04162656 A JPH04162656 A JP H04162656A
- Authority
- JP
- Japan
- Prior art keywords
- package
- hole
- lead
- package body
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004806 packaging method and process Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 230000035515 penetration Effects 0.000 abstract 4
- 239000004859 Copal Substances 0.000 abstract 1
- 229910000640 Fe alloy Inorganic materials 0.000 abstract 1
- 241000782205 Guibourtia conjugata Species 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置に関し、特にＬＳＩパッ
ケージの高密度実装に適用して有効な技術に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to high-density packaging of LSI packages.
ＬＳＩパッケージを基板に高密度に実装する方式の一つ
に、複数個のＬＳＩパッケージを基板に垂直な方向に積
み重ねて実装する多段実装方式がある。従来、Ｄ Ｉ
Ｐ （Ｄｕａｌ Ｉｎ−１ｉｎｅ Ｐａｃｋａｇｅ）、
ＳＯＪ （Ｓｍａｌｌ ０ｕｔｌｉｎｅ Ｐａｃｋａｇ
ｅ） 、Ｔ Ａ Ｂ （Ｔａｐｅ Ａｕｔｏｍａｔｅｄ
Ｂｏｎｄｉｎｇ）などを用いた種々の多段実装構造が
提案されているが、薄形化に有利なＴＡＢを用いた多段
実装構造が特に注目されている。例えば日経ＢＰ社、１
９８９年１２月１日発行の［日経マイクロデバイス」Ｐ
４８には、ＴＡＢの多段実装構造の一例として、ＳＲＡ
Ｍチップを搭載したＴＡＢを４個積層してメモリー・カ
ード用モジュールを実現したものが記載されている。One of the methods for mounting LSI packages on a board with high density is a multi-stage mounting method in which a plurality of LSI packages are stacked and mounted in a direction perpendicular to the board. Conventionally, DI
P (Dual In-1ine Package),
SOJ (Small 0utline Packag
e) , T A B (Tape Automated
Although various multi-stage mounting structures using TAB have been proposed, the multi-stage mounting structure using TAB, which is advantageous for thinning, is attracting particular attention. For example, Nikkei BP, 1
[Nikkei Microdevice] P published December 1, 989
48 shows an SRA as an example of a TAB multi-stage mounting structure.
A memory card module is described by stacking four TABs equipped with M chips.
しかし、本発明者の検討によれば、ＴＡＢを用いた多段
実装構造には下記のような問題がある。However, according to the inventor's study, the multi-stage mounting structure using TAB has the following problems.
すなわち、ＴＡＢは約３５μｍ程度の極めて薄いＣｕ箔
でリードを形成しているため、ＴＡＢを積層する工程で
リードが変形するなど、組立て工程での取り扱いに細心
の注意を必要とする煩わしさがある。また、ＴＡＢテー
プからアウターリードを打ち抜く工程が必要となるなど
、生産性の点においても問題がある。In other words, since the leads of TAB are made of extremely thin Cu foil of about 35 μm, there are problems such as deformation of the leads during the process of laminating the TAB, which requires careful handling during the assembly process. . Further, there are also problems in terms of productivity, such as the need for a step of punching out the outer leads from the TAB tape.
本発明は上記した問題点に着目してなされたものであり
、その目的はＬＳＩパッケージを高密度に実装する技術
を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique for packaging LSI packages with high density.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、次のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
本願の一発明は、半導体チップを封止したパッケージ本
体、または上記パッケージ本体から外方に延在するリー
ドに貫通孔を設け、基板に立設されたリードピンを上記
貫通孔に挿入する半導体集積回路装置の実装構造である
。One invention of the present application provides a semiconductor integrated circuit in which a through hole is provided in a package body in which a semiconductor chip is sealed or a lead extending outward from the package body, and a lead pin provided upright on a substrate is inserted into the through hole. This is the mounting structure of the device.
上記した手段によれば、基板に立設されたり一層ビンを
貫通孔に挿入することにより、ＬＳＩパッケージの多段
実装が可能となる。According to the above-mentioned means, it is possible to mount LSI packages in multiple stages by standing them up on the substrate or inserting the vias into the through holes.
第１図は、本実施例のＬＳＩパッケージの部分破断平面
図、第２図は、このＬＳＩパッケージの斜視図である。FIG. 1 is a partially cutaway plan view of the LSI package of this embodiment, and FIG. 2 is a perspective view of this LSI package.
ＬＳＩパッケージ１は、エポキシ樹脂などの合成樹脂か
らなるパッケージ本体２内に半導体チップ３を封止した
、いわゆる樹脂封止形ＬＳＩパッケージである。上記半
導体チップ３は、接着剤などによってタブ（ダイパッド
）４上に接合されている。タブ４の周囲には、所定数の
リード５が配置されており、上記リード５と半導体チッ
プ３のポンディングパッド６とは、Ａｕ５ＣｕまたはＡ
ｌからなるワイヤ７によって電気的に接続されている。The LSI package 1 is a so-called resin-sealed LSI package in which a semiconductor chip 3 is sealed within a package body 2 made of synthetic resin such as epoxy resin. The semiconductor chip 3 is bonded onto a tab (die pad) 4 using an adhesive or the like. A predetermined number of leads 5 are arranged around the tab 4, and the leads 5 and the bonding pads 6 of the semiconductor chip 3 are made of Au5Cu or A5Cu.
It is electrically connected by a wire 7 consisting of 1.
上記タブ４およびリード５は、４２アロイなどのＦｅ系
合金またはＣｕからなる。上記パッケージ本体２内に封
止されたり−ド５は、その一端がパッケージ本体２から
外方に延在することなく終端しており、いわゆるアウタ
ーリード部は存在しない。The tab 4 and lead 5 are made of Fe-based alloy such as 42 alloy or Cu. One end of the lead 5 sealed within the package body 2 is terminated without extending outward from the package body 2, and there is no so-called outer lead portion.
上記パッケージ本体２の周縁部には、パッケージ本体２
の上下面を貫通する多数の貫通孔８が所定の間隔をおい
て形成されている。上記貫通孔８の位置およびそれらの
間隔は、リード５の位置およびそれらの間隔と対応して
いる。すなわち、それぞれの貫通孔８は、対応するリー
ド５を貫通するように開孔されているので、貫通孔８の
内壁にはリード５の断面が露出している。At the periphery of the package body 2, there is a
A large number of through holes 8 are formed at predetermined intervals, penetrating the upper and lower surfaces of. The positions of the through holes 8 and the intervals therebetween correspond to the positions of the leads 5 and the intervals therebetween. That is, since each through hole 8 is opened so as to pass through the corresponding lead 5, the cross section of the lead 5 is exposed on the inner wall of the through hole 8.
第３図は、上記ＬＳＩパッケージ１の実装に用いる基板
の断面図である。FIG. 3 is a sectional view of a substrate used for mounting the LSI package 1. As shown in FIG.
ガラス布基材エポキシ樹脂（ガラエボ）などの合成樹脂
からなる基板９には、その上下面を貫通する多数のスル
ーホール１０が所定の間隔をおいて形成されている。上
記スルーホール１０の内部にはＣｕなどのメツキが施さ
れている。スルーホール１０の位置およびそれらの間隔
は、前記ＬＳＩパッケージｌの貫通孔８の位置およびそ
れらの間隔と対応している。それぞれのスルーホールｌ
Ｏの内部には、基＠９の主面に対して垂直にり一層ビン
１１が挿入されている。上記リードピン１１は、例えば
４２７０イやコバールなどのＦｅ系合金からなり、半田
などによってスルーホール１０に固定されている。リー
ドピン１１の直径は、前記ＬＳＩパッケージ１０貫通孔
８の内径よりも僅かに小さい。A large number of through holes 10 are formed at predetermined intervals in a substrate 9 made of a synthetic resin such as a glass cloth base epoxy resin (Glaevo), which penetrates the upper and lower surfaces thereof. The inside of the through hole 10 is plated with Cu or the like. The positions of the through holes 10 and their spacing correspond to the positions of the through holes 8 of the LSI package 1 and their spacing. Each through hole
Inside O, a further bottle 11 is inserted perpendicularly to the main surface of the base @9. The lead pin 11 is made of an Fe-based alloy such as 4270I or Kovar, and is fixed to the through hole 10 with solder or the like. The diameter of the lead pin 11 is slightly smaller than the inner diameter of the through hole 8 of the LSI package 10.
第４図は、上記ＬＳＩパッケージｌを基板９に多段実装
してモジュールを構成した例を示している。ＬＳＩパッ
ケージｌを基板９に多段実装するには、まず第一のＬＳ
Ｉパッケージ１の貫通孔８を基板９のリードピン１１に
挿入し、貫通孔８とリードピンＩｆとを半田や接着剤な
どにより固定する。貫通孔８の内壁にはリード５の断面
が露出しているので、上記操作により基板９のリードピ
ン１１とＬＳＩパッケージ１のリード５とが電気的に接
続される。なお、貫通孔８の内壁にメツキを施しておく
ことにより、リードピン１１とり一層５の接触面積が増
加するので、接続信頼性か向上する。FIG. 4 shows an example in which the LSI packages 1 are mounted on a board 9 in multiple stages to form a module. In order to mount the LSI packages l on the board 9 in multiple stages, the first LS
The through hole 8 of the I package 1 is inserted into the lead pin 11 of the substrate 9, and the through hole 8 and the lead pin If are fixed with solder, adhesive, or the like. Since the cross section of the lead 5 is exposed on the inner wall of the through hole 8, the lead pin 11 of the substrate 9 and the lead 5 of the LSI package 1 are electrically connected by the above operation. Note that by plating the inner wall of the through hole 8, the contact area between the lead pin 11 and the layer 5 is increased, so that connection reliability is improved.
次に、第二のＬＳＩパッケージ１の貫通孔８を基板９の
リードピン１１に挿入し、貫通孔８とリードピン１１と
を固定する。このとき、放熱を考慮して二つのＬＳＩパ
ッケージ１，１の間に適度の隙間を設ける。このように
して、所望の数のＬＳＩパッケージ１を順次リードピン
１１を挿入し、前述した方法で貫通孔７とリードピン１
０とを固定することにより、第４図に示す多段実装を実
現することができるので、ＬＳＩパッケージｌを基板９
に高密度に実装することができる。また、本実施例のＬ
ＳＩパッケージ１は、アウターリード部を有しないこと
により、その分、実装面積が縮小されているので、ＬＳ
Ｉパッケージ１の実装密度をさらに向上させることがで
きる。Next, the through holes 8 of the second LSI package 1 are inserted into the lead pins 11 of the substrate 9, and the through holes 8 and the lead pins 11 are fixed. At this time, an appropriate gap is provided between the two LSI packages 1, 1 in consideration of heat radiation. In this way, the lead pins 11 are sequentially inserted into the desired number of LSI packages 1, and the lead pins 1 are connected to the through holes 7 using the method described above.
By fixing the LSI package l to the board 9, it is possible to realize the multi-stage mounting shown in FIG.
can be mounted at high density. In addition, in this example, L
Since the SI package 1 does not have an outer lead part, the mounting area is reduced accordingly, so the SI package 1
The packaging density of the I package 1 can be further improved.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
前記実施例では、パッケージ本体に貫通孔を設けたか、
例えば第５図に示すように、パッケージ本体２の外方に
リード５を延在し、そこに貫通孔８を設けてもよい。In the above embodiments, the package body is provided with a through hole, or
For example, as shown in FIG. 5, a lead 5 may be extended outside the package body 2, and a through hole 8 may be provided therein.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
半導体チップを封止したパッケージ本体、または上記パ
ッケージ本体から外方に延在するリートに貫通孔を設け
、基板に立設されたリードピンを上記貫通孔に挿入する
ことにより、ＬＳＩパッケージの多段実装か可能となる
ので、実装密度を向上させることができる。Multi-stage mounting of LSI packages can be achieved by providing through holes in the package body in which the semiconductor chip is sealed or in the reed extending outward from the package body, and inserting lead pins set up on the substrate into the through holes. This makes it possible to improve the packaging density.
第１図は、本発明の一実施例である半導体集積回路装置
の部分破断平面図、
第２図は、この半導体集積回路装置の斜視図、第３図は
、この半導体集積回路装置の実装に用いる基板の部分断
面図、
第４図は、この半導体集積回路装置の実装構造を示す図
、
第５図は、本発明の他の実施例である半導体集積回路装
置の部分破断平面図である。
１・・・ＬＳＩパッケージ、２・・・パッケージ本体、
３・・・半導体チップ、４・・・タブ、５・・・リード
、６・・・ポンディングパッド、７・・・ワイヤ、８・
・・貫通孔、９・・・基板、１０・・・スルーホール、
１１・・・リードピン。FIG. 1 is a partially cutaway plan view of a semiconductor integrated circuit device that is an embodiment of the present invention, FIG. 2 is a perspective view of this semiconductor integrated circuit device, and FIG. 3 is a diagram showing the mounting of this semiconductor integrated circuit device. FIG. 4 is a diagram showing the mounting structure of this semiconductor integrated circuit device, and FIG. 5 is a partially cutaway plan view of a semiconductor integrated circuit device according to another embodiment of the present invention. 1...LSI package, 2...package body,
3... Semiconductor chip, 4... Tab, 5... Lead, 6... Bonding pad, 7... Wire, 8...
...Through hole, 9... Board, 10... Through hole,
11...Lead pin.
Claims (1)
記パッケージ本体から外方に延在するリードに貫通孔を
設けたことを特徴とする半導体集積回路装置。 ２、パッケージ本体に封止されたリードは、その一端が
前記パッケージ本体から外方に延在することなく終端し
ていることを特徴とする請求項１記載の半導体集積回路
装置。 ３、請求項１または２記載の半導体集積回路装置を実装
する基板にリードピンを立設し、前記リードピンを前記
貫通孔に挿入することを特徴とする半導体集積回路装置
の実装構造。[Scope of Claims] 1. A semiconductor integrated circuit device characterized in that a through hole is provided in a package body in which a semiconductor chip is sealed or in a lead extending outward from the package body. 2. The semiconductor integrated circuit device according to claim 1, wherein one end of the lead sealed in the package body is terminated without extending outward from the package body. 3. A mounting structure for a semiconductor integrated circuit device, characterized in that lead pins are provided upright on the substrate on which the semiconductor integrated circuit device according to claim 1 or 2 is mounted, and the lead pins are inserted into the through holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28704890A JPH04162656A (en) | 1990-10-26 | 1990-10-26 | Semiconductor integrated circuit device and packaging structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28704890A JPH04162656A (en) | 1990-10-26 | 1990-10-26 | Semiconductor integrated circuit device and packaging structure thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04162656A true JPH04162656A (en) | 1992-06-08 |
Family
ID=17712379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28704890A Pending JPH04162656A (en) | 1990-10-26 | 1990-10-26 | Semiconductor integrated circuit device and packaging structure thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04162656A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020028038A (en) * | 2000-10-06 | 2002-04-15 | 마이클 디. 오브라이언 | Stacking structure of semiconductor package and stacking method the same |
| WO2014097525A1 (en) * | 2012-12-19 | 2014-06-26 | 三洋電機株式会社 | Objective lens drive apparatus, optical pickup apparatus, and method for manufacturing objective lens drive apparatus |
| EP3133643A3 (en) * | 2015-01-12 | 2017-03-29 | Micronas GmbH | Integrated circuit housing |
-
1990
- 1990-10-26 JP JP28704890A patent/JPH04162656A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020028038A (en) * | 2000-10-06 | 2002-04-15 | 마이클 디. 오브라이언 | Stacking structure of semiconductor package and stacking method the same |
| WO2014097525A1 (en) * | 2012-12-19 | 2014-06-26 | 三洋電機株式会社 | Objective lens drive apparatus, optical pickup apparatus, and method for manufacturing objective lens drive apparatus |
| EP3133643A3 (en) * | 2015-01-12 | 2017-03-29 | Micronas GmbH | Integrated circuit housing |
| US9893005B2 (en) | 2015-01-12 | 2018-02-13 | Tdk-Micronas Gmbh | IC package |
| US10026684B2 (en) | 2015-01-12 | 2018-07-17 | Tdk-Micronas Gmbh | IC package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100477020B1 (en) | Multi chip package | |
| KR100621991B1 (en) | Chip scale stack package | |
| US6297547B1 (en) | Mounting multiple semiconductor dies in a package | |
| KR101070913B1 (en) | Stacked die package | |
| US6175149B1 (en) | Mounting multiple semiconductor dies in a package | |
| US8183687B2 (en) | Interposer for die stacking in semiconductor packages and the method of making the same | |
| US5894107A (en) | Chip-size package (CSP) using a multi-layer laminated lead frame | |
| JPH0685161A (en) | High density package type semiconductor device | |
| JP2002231881A (en) | Semiconductor chip package | |
| US6791166B1 (en) | Stackable lead frame package using exposed internal lead traces | |
| JP2852178B2 (en) | Film carrier tape | |
| US6903464B2 (en) | Semiconductor die package | |
| US5559305A (en) | Semiconductor package having adjacently arranged semiconductor chips | |
| JPH0430561A (en) | Semiconductor integrated circuit device and packaging structure therefor | |
| JP3497775B2 (en) | Semiconductor device | |
| US6897092B2 (en) | Method of supporting a substrate film | |
| JPH04162656A (en) | Semiconductor integrated circuit device and packaging structure thereof | |
| JPS58219757A (en) | Semiconductor device | |
| JPH01137660A (en) | Semiconductor device | |
| US6429534B1 (en) | Interposer tape for semiconductor package | |
| JP3850712B2 (en) | Multilayer semiconductor device | |
| JP2003347504A (en) | Semiconductor device and method of manufacturing the same | |
| JP2001127244A (en) | Multichip semiconductor device and method of manufacturing the same | |
| JPH02229461A (en) | Semiconductor device | |
| JP3173308B2 (en) | Semiconductor integrated circuit device |