JP6888013B2 - AL(1−x)Si(x)Oゲート絶縁体を有するエンハンスメントモードIII族窒化物デバイス - Google Patents
AL(1−x)Si(x)Oゲート絶縁体を有するエンハンスメントモードIII族窒化物デバイス Download PDFInfo
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- JP6888013B2 JP6888013B2 JP2018536814A JP2018536814A JP6888013B2 JP 6888013 B2 JP6888013 B2 JP 6888013B2 JP 2018536814 A JP2018536814 A JP 2018536814A JP 2018536814 A JP2018536814 A JP 2018536814A JP 6888013 B2 JP6888013 B2 JP 6888013B2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- H01L21/02145—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing aluminium, e.g. AlSiOx
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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Description
Claims (45)
- トランジスタであって、
III−Nチャネル層、
前記III−Nチャネル層上のIII−Nバリア層、
前記III−Nチャネル層に対して電気的に接続されたソースコンタクトとドレインコンタクト、
前記III−Nバリア層上の絶縁層、
部分的に前記絶縁層上にかつ部分的に前記III−Nチャネル層上に配置されたゲート絶縁体であって、前記ゲート絶縁体はアモルファスAl1−xSixO層を有し、0.2<x<0.8である、ゲート絶縁体、
前記ゲート絶縁体上において前記ソースコンタクトと前記ドレインコンタクトとの間に配置されたゲート電極、
を備え、
前記アモルファスAl1−xSixO層は、前記III−Nチャネル層に隣接する側にナノ結晶Al1−xSixO部分を有し、
前記トランジスタの第1部分における凹部は、前記絶縁層と前記III−Nバリア層を通過して延伸しており、
前記ゲート絶縁体は前記凹部の少なくとも一部に配置され、前記凹部において前記III−Nチャネル層と接触しており、
前記ゲート電極は、前記凹部の少なくとも一部に配置されている
ことを特徴とするトランジスタ。 - 前記アモルファスAl1−xSixO層の厚さは、1nmから100nmである
ことを特徴とする請求項1記載のトランジスタ。 - 前記ゲート電極は、半導体材料によって構成されている
ことを特徴とする請求項1記載のトランジスタ。 - 前記ゲート電極は、窒化チタニウム(TiN)、窒化インジウム(InN)、p型ポリシリコン、窒化タングステン(WN)、または酸化インジウムスズ(ITO)によって構成されている
ことを特徴とする請求項1記載のトランジスタ。 - 前記トランジスタは、off状態ブロック電圧が600V超となるように構成されている
ことを特徴とする請求項4記載のトランジスタ。 - 前記ナノ結晶Al1−xSixO部分の厚さは、前記アモルファスAl1−xSixO層の厚さの40%未満である
ことを特徴とする請求項1記載のトランジスタ。 - トランジスタであって、
III−Nチャネル層、
前記III−Nチャネル層上のIII−Nバリア層、
前記III−Nチャネル層に対して電気的に接続されたソースコンタクトとドレインコンタクト、
前記III−Nバリア層上の絶縁層、
部分的に前記絶縁層上にかつ部分的に前記III−Nチャネル層上に配置されたゲート絶縁体であって、前記ゲート絶縁体はアモルファスAl1−xSixO層を有し、0.2<x<0.8である、ゲート絶縁体、
前記ゲート絶縁体上において前記ソースコンタクトと前記ドレインコンタクトとの間に配置されたゲート電極、
を備え、
前記アモルファスAl1−xSixO層は窒素を含み、
前記トランジスタの第1部分における凹部は、前記絶縁層と前記III−Nバリア層を通過して延伸しており、
前記ゲート絶縁体は前記凹部の少なくとも一部に配置され、前記凹部において前記III−Nチャネル層と接触しており、
前記ゲート電極は、前記凹部の少なくとも一部に配置されている
ことを特徴とするトランジスタ。 - トランジスタであって、
III−Nチャネル層、
前記III−Nチャネル層上のIII−Nバリア層、
前記III−Nチャネル層に対して電気的に接続されたソースコンタクトとドレインコンタクト、
前記III−Nバリア層上の絶縁層、
前記III−Nバリア層とは別のIII−Nキャップ層であって、前記絶縁層と前記III−Nバリア層を通過して延伸する凹部において前記III−Nチャネル層上に形成された、III−Nキャップ層、
前記III−Nキャップ層上において少なくとも一部が前記凹部内に配置されているゲート絶縁体であって、アモルファスAl1−xSixO層を有し、0.2<x<0.8である、ゲート絶縁体、
前記ゲート絶縁体上に積層され少なくとも一部が前記凹部内に配置されているゲート電極であって、前記ソースコンタクトと前記ドレインコンタクトとの間に配置されている、ゲート電極、
を備え、
前記アモルファスAl1−xSixO層は、前記III−Nチャネル層に隣接する側にナノ結晶Al1−xSixO部分を有する
ことを特徴とするトランジスタ。 - 前記III−Nキャップ層はGaNを含む
ことを特徴とする請求項8記載のトランジスタ。 - 前記III−Nキャップ層は、前記III−Nチャネル層に隣接する側にAlGaNを有し、前記III−Nチャネル層の反対側にp型GaNを有する
ことを特徴とする請求項8記載のトランジスタ。 - 前記III−Nキャップ層の厚さは10nm未満である
ことを特徴とする請求項8記載のトランジスタ。 - 前記ゲート電極は半導体材料を含む
ことを特徴とする請求項8記載のトランジスタ。 - 前記ゲート電極は、窒化チタニウム(TiN)、窒化インジウム(InN)、p型ポリシリコン、窒化タングステン(WN)、または酸化インジウムスズ(ITO)によって構成されている
ことを特徴とする請求項12記載のトランジスタ。 - 前記アモルファスAl1−xSixO層の厚さは、1nmから100nmである
ことを特徴とする請求項8記載のトランジスタ。 - 前記トランジスタは、off状態ブロック電圧が600V超となるように構成されている
ことを特徴とする請求項8記載のトランジスタ。 - 前記ナノ結晶Al1−xSixO部分の厚さは、前記アモルファスAl1−xSixO層の厚さの40%未満である
ことを特徴とする請求項8記載のトランジスタ。 - 前記アモルファスAl1−xSixO層は窒素を含む
ことを特徴とする請求項8記載のトランジスタ。 - III−Nデバイスを製造する方法であって、
III−Nチャネル層上のIII−Nバリア層、前記III−Nバリア層上の絶縁層、を有する材料構造を提供するステップ、
前記デバイスの第1部分に凹部を形成するステップであって、前記凹部を形成するステップは、前記デバイスの前記第1部分において前記絶縁層と前記III−Nバリア層を除去して前記デバイスの前記第1部分において前記III−Nチャネル層を露出させるステップ、
少なくとも前記凹部の一部においてアモルファスAl1−xSixO層を形成するステップであって、前記Al1−xSixO層は前記デバイスの前記第1部分において前記チャネル層上に形成される、ステップ、
少なくとも前記凹部の一部において前記Al1−xSixO層上にゲート電極を形成するステップであって、前記ゲート電極は複合半導体材料と金属を含むステップ、
を有し、
前記アモルファスAl1−xSixO層は、前記III−Nチャネル層に隣接する側にナノ結晶Al1−xSixO部分を有する
ことを特徴とする方法。 - 前記アモルファスAl1−xSixO層を形成するステップは、有機金属気相成長法(MOCVD)成長リアクタを用いて実施される
ことを特徴とする請求項18記載の方法。 - 前記方法はさらに、高温において前記III−Nデバイスをアニーリングするステップを有する
ことを特徴とする請求項18記載の方法。 - 前記アモルファスAl1−xSixO層を形成するステップと前記III−Nデバイスをアニーリングするステップは、MOCVD成長リアクタにおいて空気に露出させることなく順次実施される
ことを特徴とする請求項20記載の方法。 - 前記III−Nデバイスをアニーリングするステップは、800℃以上の温度で実施される
ことを特徴とする請求項20記載の方法。 - 前記ゲート電極の前記複合半導体材料は、窒化チタニウム(TiN)、窒化インジウム(InN)、p型ポリシリコン、窒化タングステン(WN)、または酸化インジウムスズ(ITO)を含む
ことを特徴とする請求項18記載の方法。 - 前記方法はさらに、前記ゲート電極を形成した後、フォーミングガス内で前記III−Nデバイスをアニーリングするステップを有する
ことを特徴とする請求項18記載の方法。 - 前記アニーリングは、350℃以上の温度で実施される
ことを特徴とする請求項24記載の方法。 - 前記アモルファスAl1−xSixOを形成するステップは、500℃以上の積層温度で実施される
ことを特徴とする請求項18記載の方法。 - 前記ナノ結晶Al1−xSixO部分の厚さは、前記アモルファスAl1−xSixO層の厚さの40%未満である
ことを特徴とする請求項18記載の方法。 - 前記アモルファスAl1−xSixO層を形成するステップは、前記アモルファスAl1−xSixO層に対して窒素を組み込むステップを有する
ことを特徴とする請求項18記載の方法。 - III−Nデバイスを製造する方法であって、
III−Nチャネル層上のIII−Nバリア層、前記III−Nバリア層上の絶縁層、を有する材料構造を提供するステップ、
前記デバイスの第1部分に凹部を形成するステップであって、前記凹部を形成するステップは、前記デバイスの前記第1部分において前記絶縁層と前記III−Nバリア層を除去して前記デバイスの前記第1部分において前記III−Nチャネル層を露出させるステップ、
前記III−Nチャネル層上において前記凹部内にIII−Nキャップ層を形成するステップ、
前記凹部内の少なくとも一部にアモルファスAl1−xSixO層を形成するステップであって、前記アモルファスAl1−xSixO層は前記デバイスの前記第1部分において前記III−Nキャップ層上に形成される、ステップ、
前記Al1−xSixO層上において前記凹部の少なくとも一部にゲート電極を形成するステップであって、前記ゲート電極は複合半導体材料を有する、ステップ、
を有し、
前記アモルファスAl1−xSixO層は、前記III−Nチャネル層に隣接する側にナノ結晶Al1−xSixO部分を有する
ことを特徴とする方法。 - 前記方法はさらに、前記アモルファスAl1−xSixO層を形成した後、酸素を含むガス環境下で高温において前記III−Nデバイスをアニーリングするステップを有する ことを特徴とする請求項29記載の方法。
- 前記方法はさらに、前記チャネル層と電気的に接続されたソースコンタクトとドレインコンタクトを形成するステップを有し、前記ゲート電極は前記ソースコンタクトと前記ドレインコンタクトとの間に配置される
ことを特徴とする請求項30記載の方法。 - 前記III−Nキャップ層を形成するステップと前記アモルファスAl1−xSixO層を形成するステップは、金属有機気相成長法(MOCVD)によって実施される
ことを特徴とする請求項29記載の方法。 - 前記III−Nキャップ層を形成するステップと前記アモルファスAl1−xSixO層を形成するステップは、MOCVD成長リアクタにおいて空気に露出させることなく順次実施される
ことを特徴とする請求項32記載の方法。 - 前記III−Nキャップ層を形成するステップ、前記アモルファスAl1−xSixO層を形成するステップ、前記III−Nデバイスをアニーリングするステップは、成長リアクタにおいてそのまま実施される
ことを特徴とする請求項33記載の方法。 - 前記III−Nキャップ層を形成するステップは、前記III−Nキャップ層を形成する前にMgプリカーソルガスを流し、前記III−Nキャップ層を形成する間はMgガスを流さないステップを有する
ことを特徴とする請求項32記載の方法。 - 前記ゲート電極の前記複合半導体材料は、窒化チタニウム(TiN)、窒化インジウム(InN)、p型ポリシリコン、窒化タングステン(WN)、または酸化インジウムスズ(ITO)を含む
ことを特徴とする請求項29記載の方法。 - 前記III−Nデバイスをアニーリングするステップは、800℃以上の温度で実施される
ことを特徴とする請求項30記載の方法。 - 前記III−Nキャップ層の厚さは1から10nmの範囲である
ことを特徴とする請求項29記載の方法。 - 前記III−Nキャップ層はAlGaNを含む
ことを特徴とする請求項29記載の方法。 - 前記III−Nキャップ層は、前記III−Nチャネル層に隣接する側にAlGaNを有し、前記III−Nチャネル層の反対側にp型GaNを有する
ことを特徴とする請求項29記載の方法。 - 前記デバイスの前記第1部分において前記凹部を形成するステップは、ドライエッチングにより前記デバイスの前記第1部分において前記絶縁層と前記III−Nバリア層を除去するステップを有する
ことを特徴とする請求項29記載の方法。 - 前記デバイスの前記第1部分において前記凹部を形成するステップはさらに、前記デバイスの前記第1部分において前記III−Nチャネル層を部分的にエッチングするステップを有する
ことを特徴とする請求項41記載の方法。 - 前記III−Nチャネル層の部分的なエッチングは5nm未満である
ことを特徴とする請求項42記載の方法。 - 前記方法はさらに、前記ゲート電極を形成した後、フォーミングガス内で前記III−Nデバイスをアニーリングするステップを有する
ことを特徴とする請求項29記載の方法。 - 前記アニーリングは、350℃以上の温度で実施される
ことを特徴とする請求項44記載の方法。
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