JP6480860B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6480860B2 JP6480860B2 JP2015508330A JP2015508330A JP6480860B2 JP 6480860 B2 JP6480860 B2 JP 6480860B2 JP 2015508330 A JP2015508330 A JP 2015508330A JP 2015508330 A JP2015508330 A JP 2015508330A JP 6480860 B2 JP6480860 B2 JP 6480860B2
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Description
実施の形態1にかかる半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置の構造を示す断面図である。図1に示すように、実施の形態1にかかる半導体装置は、nドレイン領域となるSiC基板1のおもて面上にn-ドリフト層となるn-エピタキシャル層2を堆積してなるエピタキシャル基板を用いて作製(製造)されたSiC−MOSFETである。エピタキシャル基板のおもて面側(n-エピタキシャル層2側)の表面層には、pベース領域3が選択的に設けられている。また、エピタキシャル基板のおもて面上には、n-エピタキシャル層2の、隣り合うpベース領域3に挟まれた部分からpベース領域3にわたってpエピタキシャル層4が堆積されている。
次に、実施例1にかかる半導体装置のゲートしきい値電圧Vthについて説明する。図3は、実施例1にかかる半導体装置のゲートしきい値電圧について示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがい、SiC−MOSFETを作製した(以下、実施例1とする)。実施例1は、ステップS17の工程において無電解NiPめっき処理により第1金属膜21としてNiPめっき膜を形成し、ステップS18の工程においてN2雰囲気のアニールを行っている(めっきあり・アニールあり)。第1金属膜21の面積比率(=S2/S1)を46%とした。
次に、第1金属膜21の膜厚とゲートしきい値電圧低下量ΔVthとの関係について説明する。図4は、実施例2にかかる半導体装置の第1金属膜の膜厚とゲートしきい値電圧低下量との関係を示す特性図である。上述した実施の形態1にかかる半導体装置の製造方法にしたがい、第1金属膜21の膜厚の異なる複数のSiC−MOSFETを作製した(以下、実施例2とする)。具体的には、実施例2として、第1金属膜21の膜厚がそれぞれ1μm、4.5μmおよび10μmの3つの試料を用意した。実施例2の第1金属膜21の膜厚以外の構成は、実施例1と同様である。
次に、めっき前処理とゲートしきい値電圧低下量ΔVthとの関係について説明する。図5は、実施例3の無電解NiPめっき処理条件を示す図表である。図6は、実施例3にかかる半導体装置の第1金属膜におけるめっき前処理とゲートしきい値電圧低下量との関係を示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがい、めっき前処理工程の一部の工程を省略した複数のSiC−MOSFETを作製した(以下、実施例3とする)。具体的には、実施例3として、めっき前処理を異なるタイミングで終了した後、ステップS17の工程を行わずにステップS18を行った3つの試料を用意した。
次に、第1金属膜21の構成材料とゲートしきい値電圧低下量ΔVthとの関係について説明する。図7は、実施例4の無電解Cuめっき処理条件を示す図表である。図8は、実施例4にかかる半導体装置の第1金属膜の構成材料とゲートしきい値電圧との関係を示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがい、第1金属膜21としてCuめっき膜を形成したSiC−MOSFETを作製した(以下、実施例4とする)。
次に、第1金属膜21の面積比率とゲートしきい値電圧低下量ΔVthとの関係について説明する。図9は、実施例5,9にかかる半導体装置の第1金属膜の面積比率とゲートしきい値電圧低下量との関係を示す特性図である。図10は、実施例5にかかる半導体装置の第1金属膜の配置を示す平面図である。実施の形態1にかかる半導体装置の製造方法にしたがい、第1金属膜21の面積比率を10%以上とした複数のSiC−MOSFETを作製した(以下、実施例5とする)。具体的には、実施例5として、第1金属膜21の面積比率を10%、20%、30%、46%、74%および90%とした各試料を用意した。
次に、ステップS18のアニールの雰囲気とゲートしきい値電圧低下量ΔVthとの関係について説明する。図11は、実施例6にかかる半導体装置のアニールの雰囲気とゲートしきい値電圧低下量との関係を示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがって、ステップS18のアニールの雰囲気を種々変更して複数のSiC−MOSFETを作製した(以下、実施例6とする)。具体的には、実施例6として、N2ガス雰囲気、真空雰囲気およびAr雰囲気においてステップS18のアニールを行った3つの試料を用意した。
次に、ステップS18のアニール温度およびアニール時間とゲートしきい値電圧低下量ΔVthとの関係について説明する。図12は、実施例7−1にかかる半導体装置のアニール温度およびアニール時間とゲートしきい値電圧低下量との関係を示す特性図である。図13は、実施例7−2にかかる半導体装置のアニール温度およびアニール時間とゲートしきい値電圧低下量との関係を示す特性図である。実施の形態1にかかる半導体装置の製造方法にしたがって、ステップS18のアニール温度およびアニール時間を種々変更して複数のSiC−MOSFETを作製した(以下、実施例7とする)。
次に、実施の形態2にかかる半導体装置の製造方法について説明する。図14は、実施の形態2にかかる半導体装置の製造方法の概要を示すフローチャートである。実施の形態2にかかる半導体装置の製造方法が実施の形態1にかかる半導体装置の製造方法と異なる点は、おもて面電極13を形成した(ステップS13)後、パッシベーション膜を形成する(ステップS14)前に、第1アニール(ステップS19)を行う点である。第1アニールのアニール温度は、ステップS18のアニール(以下、第2アニールとする)のアニール温度よりも高く、例えば350℃以上であってもよい。第1アニールのアニール温度以外の条件は、第2アニールと同様であってもよい。
次に、実施例8にかかる半導体装置のゲートしきい値電圧低下量ΔVthについて説明する。図15は、実施例8にかかる半導体装置のゲートしきい値電圧低下量について示す特性図である。実施の形態2にかかる半導体装置の製造方法にしたがい、SiC−MOSFETを作製した(以下、実施例8とする)。実施例8は、ステップS19の第1アニールを行う以外は実施例1と同様である。すなわち、実施例8においては、おもて面電極13の形成後に第1アニールを行い、かつ第1金属膜21の形成後に第2アニールを行っている。
次に、第1金属膜21の面積比率とゲートしきい値電圧低下量ΔVthとの関係について説明する。実施の形態2にかかる半導体装置の製造方法にしたがい、第1金属膜21の面積比率を46%以上とした複数の実施例9−1,9−2を作製した。具体的には、実施例9−1,9−2として、第1金属膜21の面積比率を46%、74%および90%とした各試料を用意した。第1アニールは、350℃の温度で1時間とした。第2アニールは、300℃の温度で3時間とした。第1金属膜21の面積比率の調整方法は実施例5と同様である。
2 n-エピタキシャル層
3 pベース領域
4 pエピタキシャル層
5 n++ソース領域
6 p+コンタクト領域
7 n打ち返し領域
8 ゲート絶縁膜
9 ゲート電極
10 層間絶縁膜
11 TiN膜
12 Ni膜
13 おもて面電極
14 コンタクト金属膜
15 裏面電極
21 第1金属膜
22 第2金属膜
23 パッシベーション膜
23a ソースパッドコンタクトホール
25 絶縁膜
S1 おもて面電極の表面積
S2 第1金属膜の表面積
Claims (6)
- 炭化珪素基板のおもて面にゲート絶縁膜およびゲート電極からなる絶縁ゲート構造を形成する第1工程と、
前記炭化珪素基板のおもて面に、層間絶縁膜によって前記ゲート電極と絶縁された、アルミニウムまたはアルミニウム合金からなるおもて面電極を形成する第2工程と、
前記おもて面電極の表面に、ニッケル、ニッケル合金、銅、パラジウム、チタン、白金、金または銀からなる金属膜、または、これらの金属からなる金属膜を2層以上積層してなる金属積層膜を形成する第3工程と、
前記第3工程の後、窒素ガス雰囲気、窒素を含む混合ガス雰囲気、真空雰囲気またはアルゴンガス雰囲気のアニールを行う第4工程と、
を含み、
前記第3工程は、
前記炭化珪素基板のおもて面および前記おもて面電極の表面をパッシベーション膜で覆う保護工程と、
前記パッシベーション膜に、前記おもて面電極の表面の60%以上90%以下の範囲を露出するコンタクトホールを形成する開口工程と、
前記おもて面電極の、前記コンタクトホールに露出する表面全面に、めっき法により前記金属膜または前記金属積層膜を形成する金属膜形成工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記第2工程後、前記第3工程前に、窒素ガス雰囲気、窒素を含む混合ガス雰囲気、真空雰囲気またはアルゴンガス雰囲気のアニールを行う第5工程をさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第5工程のアニール温度は、前記第4工程のアニール温度よりも高いことを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記第5工程のアニール温度は、350℃以上であることを特徴とする請求項2または3に記載の半導体装置の製造方法。
- 前記第4工程のアニール温度は、150℃以上450℃以下であることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置の製造方法。
- 前記第4工程のアニール温度は、300℃以上420℃以下であることを特徴とする請求項5に記載の半導体装置の製造方法。
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JP6297783B2 (ja) * | 2013-03-08 | 2018-03-20 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP6069059B2 (ja) * | 2013-03-22 | 2017-01-25 | 住友電気工業株式会社 | 炭化珪素半導体装置 |
EP3043376B1 (en) * | 2013-09-05 | 2021-03-03 | Fuji Electric Co., Ltd. | Method for manufacturing silicon carbide semiconductor element |
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