JP6244177B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6244177B2 JP6244177B2 JP2013233622A JP2013233622A JP6244177B2 JP 6244177 B2 JP6244177 B2 JP 6244177B2 JP 2013233622 A JP2013233622 A JP 2013233622A JP 2013233622 A JP2013233622 A JP 2013233622A JP 6244177 B2 JP6244177 B2 JP 6244177B2
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- drain
- trench isolation
- mos transistor
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- 239000004065 semiconductor Substances 0.000 title claims description 18
- 210000000746 body region Anatomy 0.000 claims description 37
- 238000002955 isolation Methods 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 10
- 238000001514 detection method Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 description 15
- 230000005684 electric field Effects 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Description
前記ボディ領域に対して隣接又は離間して完全に包含する第2導電型のドレインドリフト領域と、前記ドレインドリフト領域に接する第2導電型のドレイン領域と、前記ボディ領域内に形成される第2導電型のソース領域と、前記ソース領域端から前記ドレインドリフト領域上を覆う絶縁膜と、前記絶縁膜を介して前記ソース領域端上から前記ドレインドリフト領域上までを覆うゲート電極と、前記、ボディ領域とドレインドリフト領域の端部に隣接する絶縁膜で構成されたトレンチ分離が備えられていて、前記トレンチ分離に隣接する第1導電型の第2のボディ領域と、前記トレンチ分離に隣接する第2導電型の第2のドレインドリフト領域と、前記ドレインドリフト領域に接する第2導電型の第2のドレイン領域と、前記ボディ領域内に形成される第2導電型の第2のソース領域と、前記第2のソース領域端から前記第2のドレインドリフト領域上を覆う第2の絶縁膜と、前記第2の絶縁膜を介して前記第2の第ソース領域上から前記第2のドレインドリフト領域上までを覆う第2のゲート電極とで構成されるダミーMOSトランジスタを具備している。また、前記ダミーMOSトランジスタの第2のボディ領域、第2のドレインドリフト領域はそれぞれMOSトランジスタのボディ領域、ドレインドリフト領域と同一の不純物プロファイルを持つ共に、前記ダミーMOSトランジスタの第2のソース領域、第2のドレイン領域との距離はMOSトランジスタのソース領域、ドレイン領域との距離と少なくともトレンチ分離に接する部分は等しくなっている。また、前記ダミーMOSトランジスタのソース電極、ドレイン電極はMOSトランジスタのソース電極、ドレイン電極と配線層を介して電気的に接続されていると共に、前記ダミーMOSトランジスタのゲート電極は、ソース電極と電気的に接続されている。
(実施の形態1)
本発明の第1の実施形態を図1〜図2に基づいて説明する。
図1は、第1の実施形態を説明するための平面図、図2(a)、(b)、(c)は、図1のA−A’線、B−B’線、C−C’線のそれぞれの断面図を示している。
(実施の形態2)
本発明の第2の実施形態を図3に基づいて説明する。図1の構成と異なる点は、図1はMOSトランジスタ11のゲート電極3がダイオード12のドレインフィールドプレート電極7は配線層を介して接続されているのに対し、図3ではゲート電極3がドレインフィールドプレート電極と直接接続されている点である。これにより、第1の実施形態で述べた事と同様な効果が得られる。
(実施の形態3)
本発明の第3の実施形態を図4に基づいて説明する。図3の構成と異なる点は、MOSトランジスタ11のN+ドレイン領域5とN型ドレインドリフト領域4の周りにゲート電極3、N型ソース領域2があり、それに対応して、ダイオード12のN型カソード領域8の周りにP+アノード・コンタクト拡散領域がある点である。これにより、第1の実施形態で述べたように、トランジスタに電圧を加えた時のトレンチ分離10bに加わる電界強度は0となり、同様な効果が得られる。
(実施の形態4)
本発明の第4の実施形態を図5〜図6に基づいて説明する。図1の構成と異なる点はトレンチ分離10bに隣接してダイオード12の代わりにダミーMOSトランジスタ18がある点である。MOSトランジスタ11の断面構造(図6(b)はダミーMOSトランジスタ18の断面構造(図6(c))は少なくともトレンチ分離10bに近接する部分は同じとなっている。また、図には記載されていないが、N+ドレイン領域5とダミーMOSトランジスタ18のN+ドレイン領域22は配線層を介して電気的に接続され、P+ボディ・コンタクト拡散領域15とダミーMOSトランジスタ18のP+ボディ・コンタクト拡散領域24、ダミーMOSトランジスタ18のゲート電極20は配線層を介して電気的に接続されている。これにより、MOSトランジスタ11に電圧を加えた時のP型ボディ領域1、N型ドレインドリフト領域4の電界ポテンシャルをダミーMOSトランジスタの電界ポテンシャルと少なくともトレンチ分離10bに近接する部分を同一にでき、トレンチ分離10bに加わる電界強度は0となる。これにより、第1の実施形態で述べた効果が得られる。
Claims (1)
- 半導体基板上に形成される横型半導体デバイスであって、
前記半導体基板層に形成される第1のP型ボディ領域と、
前記第1のP型ボディ領域に対して隣接又は離間して完全に包含する第1のN型ドレインドリフト領域と、
前記第1のN型ドレインドリフト領域に接する第1のN型ドレイン領域と、
前記第1のP型ボディ領域内に形成される第1のN型のソース領域と、
前記第1のP型ボディ領域と前記第1のN型ドレインドリフト領域の端部に隣接する絶縁膜で構成されたトレンチ分離部を備えたMOSトランジスタ領域と、
前記トレンチ分離部に隣接する第2のP型ボディ領域と、
前記トレンチ分離部に隣接する第2のN型ドレインドリフト領域と、
前記第2のN型ドレインドリフト領域に接する第2のN型ドレイン領域と、
前記第2のP型ボディ領域内に形成される第2のN型ソース領域と、
前記第2のN型ソース領域端上から前記第2のN型ドレインドリフト領域上までを覆うゲート電極とを備えたダミーMOSトランジスタ領域と、を有し、
前記第2のP型ボディ領域、前記第2のN型ドレインドリフト領域はそれぞれ、前記第1のP型ボディ領域、前記第1のN型ドレインドリフト領域と同一の不純物プロファイルを持ち、
前記トレンチ分離部に接する部分の前記第2のN型ソース領域と前記第2のN型ドレイン領域との距離は、前記トレンチ分離部に接する部分の前記第1のN型ソース領域と前記第1のN型ドレイン領域との距離と等しくなっており、
前記第2のN型ソース領域、前記第2のN型ドレイン領域はそれぞれ、前記第1のN型ソース領域、前記第1のN型ドレイン領域と配線層を介して電気的に接続されており、さらに前記ゲート電極は前記第2のN型ソース領域と接続され、
当該横型半導体デバイスは、電流検出回路に搭載されることを特徴とする横型半導体デバイス。
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