JP4342498B2 - 横型半導体デバイス - Google Patents
横型半導体デバイス Download PDFInfo
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- JP4342498B2 JP4342498B2 JP2005285726A JP2005285726A JP4342498B2 JP 4342498 B2 JP4342498 B2 JP 4342498B2 JP 2005285726 A JP2005285726 A JP 2005285726A JP 2005285726 A JP2005285726 A JP 2005285726A JP 4342498 B2 JP4342498 B2 JP 4342498B2
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- 239000004065 semiconductor Substances 0.000 title claims description 17
- 210000000746 body region Anatomy 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 description 21
- 238000009792 diffusion process Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 230000020169 heat generation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
支持基板1の上に埋め込み酸化膜2を介して半導体層3が形成されている。半導体層3の表面には、N型ボディ領域4、P+ドレイン領域9が形成されている。更に、N型ボディ領域4の表面には、P+ソース領域8、N+ボディ・コンタクト拡散領域10が形成される。また、N型ボディ領域4の端部に重なってゲート酸化膜6を介してゲート電極7が形成されている。
通常、オン耐圧を向上するために、平面レイアウトとして2つの従来例が考えられる。
第1の従来例は、図4の平面図に示すように、P+ドレイン領域9をN型ボディ領域4で完全に包囲している構造である。更に、P+ドレイン領域9の端部を包囲する環状のN型ボディ領域4の表面のP+ソース領域8を削除する。この構造は、特許文献1に示されているように、ドレイン端近傍での電流密度を低減できるためオン耐圧を向上できる。
第1は、図6に示すようにドレイン電圧−電流特性において負性抵抗領域が見られることである。約140ボルトからドレイン電流が低下する傾向が見られる。このような負性抵抗領域は発熱に起因するため、印加条件や放熱性によっても変化する不安定な現象な現象であり、できれば無くす、又は低減することが望ましい。
ボディ領域端において、ゲート電極とソース領域が絶縁膜を介して隣接していないため、MOSトランジスタ動作はおきず、端部を経由する電流を低減できる。このため、端部での発熱を抑制することができる。オン耐圧が高くて発熱の影響を受けにくく安定したドレイン電圧−電流特性を得ることができる。
(第1の実施形態)
図1は、本発明の第1の実施形態の高耐圧PchMOSトランジスタを示す。
図2は、本発明の第2の実施形態の高耐圧NchMOSトランジスタを示す。
図2に示すように、第1の実施形態と同様に、N+ソース領域12、P型ボディ領域11およびP+ボディ・コンタクト拡散領域14を、N+ドレイン領域15およびN型ドリフト領域13で包囲している。また、P型ボディ領域11の端部に重なってゲート電極16が形成されている。そして、前記P型ボディ領域11の端部は、半円状の平面形状をしており、その直径Aは14〜18μmの範囲である。一方、端部から離れた直線状の中央部の幅Bは10μmである。オフ耐圧は、ボディ領域端の直径が中央部の幅と同じ場合は、175ボルトであるが、ボディ領域端の直径を中央部に比べて長くした場合は180ボルトまで上昇した。
また、ボディ領域端部にソース領域と同じ導電型の拡散層を形成してゲート電極と隣接しても、中央部のソース領域と電気的に接続されていなければソース領域としての機能を果たすことはできず本発明のデバイス構造に含まれる。
また、本発明の各実施形態では、高耐圧MOSトランジスタの製造方法について、特に説明していないが、例えば特許文献1に記載される方法を用いて製造することができる。
2 埋め込み酸化膜
3 半導体層
4 N型ボディ領域
5 P型ドリフト領域
6 ゲート酸化膜
7 ゲート電極
8 P+ソース領域
9 P+ドレイン領域
10 N+ボディ・コンタクト拡散領域
11 P型ボディ領域
12 N+ソース領域
13 N型ドリフト領域
14 P+ボディ・コンタクト拡散領域
15 N+ドレイン領域
Claims (2)
- 支持基板上に埋め込み絶縁膜を介して接続する半導体層に形成される横型半導体デバイスであって、
前記半導体層に形成される第1導電型のボディ領域と、
前記ボディ領域に対して隣接又は離間して完全に包囲する第2導電型のドリフト領域と、
前記ボディ領域から離間してかつ前記ドリフト領域に接する第2導電型のドレイン領域と、
前記ボディ領域内に形成され該端部から離間する第2導電型のソース領域と、
前記半導体層上に形成され少なくとも前記ソース領域端から前記ドレイン領域端までを覆う絶縁膜と、
前記絶縁膜を介して前記ソース領域端上方から前記ドリフト領域上方までを覆うゲート電極と、
前記ソース領域、前記ボディ領域および前記ドレイン領域には、それぞれ接続する電極が備えられて、
前記ボディ領域の平面形状は、少なくとも矩形状の中央部と半円状の端部とで構成され、該端部では前記ゲート電極と前記ソース領域とが前記絶縁膜を介して隣接していないことを特徴とする横型半導体デバイス。 - 前記端部の直径は、前記中央部の幅よりも大きいことを特徴とする
請求項1記載の横型半導体デバイス。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005285726A JP4342498B2 (ja) | 2005-09-30 | 2005-09-30 | 横型半導体デバイス |
US11/488,154 US7323747B2 (en) | 2005-09-30 | 2006-07-18 | Lateral semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005285726A JP4342498B2 (ja) | 2005-09-30 | 2005-09-30 | 横型半導体デバイス |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007096143A JP2007096143A (ja) | 2007-04-12 |
JP2007096143A5 JP2007096143A5 (ja) | 2008-03-21 |
JP4342498B2 true JP4342498B2 (ja) | 2009-10-14 |
Family
ID=37901095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005285726A Expired - Fee Related JP4342498B2 (ja) | 2005-09-30 | 2005-09-30 | 横型半導体デバイス |
Country Status (2)
Country | Link |
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US (1) | US7323747B2 (ja) |
JP (1) | JP4342498B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI699464B (zh) | 2017-03-31 | 2020-07-21 | 日商Jx金屬股份有限公司 | 化合物半導體及化合物半導體單晶之製造方法 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5515248B2 (ja) * | 2008-03-26 | 2014-06-11 | 富士電機株式会社 | 半導体装置 |
JP2010278312A (ja) * | 2009-05-29 | 2010-12-09 | Sanyo Electric Co Ltd | 半導体装置 |
US8749223B2 (en) * | 2011-06-22 | 2014-06-10 | Nxp B.V. | Galvanic isolation device and method |
US9269704B2 (en) | 2012-05-15 | 2016-02-23 | Nuvoton Technology Corporation | Semiconductor device with embedded silicon-controlled rectifier |
JP6244177B2 (ja) | 2013-11-12 | 2017-12-06 | 日立オートモティブシステムズ株式会社 | 半導体装置 |
US9153691B1 (en) * | 2014-07-22 | 2015-10-06 | Qualcomm Incorporated | High voltage MOS transistor |
US9362356B2 (en) * | 2014-11-12 | 2016-06-07 | Analog Devices Global | Transistor |
US10784372B2 (en) * | 2015-04-03 | 2020-09-22 | Magnachip Semiconductor, Ltd. | Semiconductor device with high voltage field effect transistor and junction field effect transistor |
US20170194350A1 (en) * | 2015-12-30 | 2017-07-06 | Stmicroelectronics (Crolles 2) Sas | Low-noise mos transistors and corresponding circuit |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US5258636A (en) * | 1991-12-12 | 1993-11-02 | Power Integrations, Inc. | Narrow radius tips for high voltage semiconductor devices with interdigitated source and drain electrodes |
JP2822961B2 (ja) * | 1995-12-14 | 1998-11-11 | 日本電気株式会社 | 半導体装置 |
US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
JP3473460B2 (ja) | 1998-11-20 | 2003-12-02 | 富士電機株式会社 | 横型半導体装置 |
JP4534303B2 (ja) * | 2000-04-27 | 2010-09-01 | 富士電機システムズ株式会社 | 横型超接合半導体素子 |
US7115946B2 (en) * | 2000-09-28 | 2006-10-03 | Kabushiki Kaisha Toshiba | MOS transistor having an offset region |
US6982461B2 (en) * | 2003-12-08 | 2006-01-03 | Semiconductor Components Industries, L.L.C. | Lateral FET structure with improved blocking voltage and on resistance performance and method |
-
2005
- 2005-09-30 JP JP2005285726A patent/JP4342498B2/ja not_active Expired - Fee Related
-
2006
- 2006-07-18 US US11/488,154 patent/US7323747B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI699464B (zh) | 2017-03-31 | 2020-07-21 | 日商Jx金屬股份有限公司 | 化合物半導體及化合物半導體單晶之製造方法 |
JP7321929B2 (ja) | 2017-03-31 | 2023-08-07 | Jx金属株式会社 | ZnドープInP単結晶基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070075393A1 (en) | 2007-04-05 |
JP2007096143A (ja) | 2007-04-12 |
US7323747B2 (en) | 2008-01-29 |
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