JP6092645B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6092645B2 JP6092645B2 JP2013022649A JP2013022649A JP6092645B2 JP 6092645 B2 JP6092645 B2 JP 6092645B2 JP 2013022649 A JP2013022649 A JP 2013022649A JP 2013022649 A JP2013022649 A JP 2013022649A JP 6092645 B2 JP6092645 B2 JP 6092645B2
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- JP
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- Prior art keywords
- lead
- island
- semiconductor device
- mold resin
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
フラットパッケージの基本的な構造が特許文献1、2に記されている。
また、リードとモールド樹脂底面に段差を付けられない場合は、半導体パッケージ底面から露出したリード周囲のモールド樹脂に凹部を形成する。
半導体パッケージ裏面放熱板に凹部を形成し、半田との接合面積を広げることで、半導体パッケージと回路基板の半田実装強度を向上させる。
図4に示すとおり、リード1の周辺に沿って「コの字形」にモールド樹脂部6に凹部7を形成することで、回路基板へ印刷した半田の平面的なズレ(X方向、Y方向)に対してセルフアライメント効果を出すことができる。
図9は図8に示した半導体パッケージを裏面から見た図である。
図12は図11に示した半導体装置の裏面図である。
2 アイランド裏面凹部
3 アイランド
4 半導体チップ
5 ワイヤー
6 モールド樹脂
7 モールド樹脂凹部
8 下段リード
11 リードの外側面
12 リードの内側面
Claims (3)
- アイランドに搭載された半導体チップと、
前記アイランドと離間して配置され、前記半導体チップとワイヤーを介して接続したリードと、
前記アイランドと前記半導体チップと前記ワイヤーと前記リードを封止した絶縁性樹脂と、
からなる、前記リードの底面を前記絶縁性樹脂から露出したリードフラットタイプの半導体装置であって、
前記絶縁性樹脂の前記リードに隣接する部分に形成され、前記絶縁性樹脂の底面の下に位置する前記リードの内側面を露出した第一の凹部と前記アイランドの周囲に隣接する絶縁性樹脂に設けられた第二の凹部とは分離され、前記リードに隣接する第一の凹部と前記アイランドに隣接する第二の凹部との間には前記絶縁性樹脂からなる凸部が設けられていることを特徴とする半導体装置。 - 前記絶縁性樹脂から露出する前記アイランド裏面に第三の凹部を設けたことを特徴とする請求項1記載の半導体装置。
- 前記第一乃至前記第三の凹部のいずれかひとつの深さは、0.01から0.05mmであることを特徴とする請求項1または2記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013022649A JP6092645B2 (ja) | 2013-02-07 | 2013-02-07 | 半導体装置 |
TW103102116A TWI588948B (zh) | 2013-02-07 | 2014-01-21 | Flat pin type semiconductor device |
CN201410037891.8A CN103985675B (zh) | 2013-02-07 | 2014-01-26 | 半导体装置 |
US14/172,247 US9397026B2 (en) | 2013-02-07 | 2014-02-04 | Semiconductor device having flat leads |
KR1020140013452A KR102145167B1 (ko) | 2013-02-07 | 2014-02-06 | 반도체 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013022649A JP6092645B2 (ja) | 2013-02-07 | 2013-02-07 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014154689A JP2014154689A (ja) | 2014-08-25 |
JP6092645B2 true JP6092645B2 (ja) | 2017-03-08 |
Family
ID=51258611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013022649A Expired - Fee Related JP6092645B2 (ja) | 2013-02-07 | 2013-02-07 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9397026B2 (ja) |
JP (1) | JP6092645B2 (ja) |
KR (1) | KR102145167B1 (ja) |
CN (1) | CN103985675B (ja) |
TW (1) | TWI588948B (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ITTO20120854A1 (it) * | 2012-09-28 | 2014-03-29 | Stmicroelectronics Malta Ltd | Contenitore a montaggio superficiale perfezionato per un dispositivo integrato a semiconduttori, relativo assemblaggio e procedimento di fabbricazione |
JP6357371B2 (ja) * | 2014-07-09 | 2018-07-11 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
JP6494465B2 (ja) * | 2015-08-03 | 2019-04-03 | エイブリック株式会社 | 半導体装置の製造方法 |
JP7484770B2 (ja) * | 2021-02-26 | 2024-05-16 | 三菱電機株式会社 | 半導体パッケージ |
JP2023036447A (ja) * | 2021-09-02 | 2023-03-14 | 新電元工業株式会社 | リードフレーム一体型基板、半導体装置、リードフレーム一体型基板の製造方法、及び半導体装置の製造方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
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US4827611A (en) * | 1988-03-28 | 1989-05-09 | Control Data Corporation | Compliant S-leads for chip carriers |
JP2521518B2 (ja) * | 1988-06-30 | 1996-08-07 | 松下電子工業株式会社 | 半導体集積回路パッケ―ジ |
EP0569949A3 (en) * | 1992-05-12 | 1994-06-15 | Akira Kitahara | Surface mount components and semifinished products thereof |
US5286999A (en) * | 1992-09-08 | 1994-02-15 | Texas Instruments Incorporated | Folded bus bar leadframe |
US5604376A (en) * | 1994-06-30 | 1997-02-18 | Digital Equipment Corporation | Paddleless molded plastic semiconductor chip package |
KR980006174A (ko) * | 1996-06-18 | 1998-03-30 | 문정환 | 버틈 리드 패키지 |
US6211462B1 (en) * | 1998-11-05 | 2001-04-03 | Texas Instruments Incorporated | Low inductance power package for integrated circuits |
JP2000299400A (ja) | 1999-04-14 | 2000-10-24 | Sony Corp | ノンリード・フラットパッケージ型半導体装置 |
JP2000332162A (ja) * | 1999-05-18 | 2000-11-30 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
MY133357A (en) * | 1999-06-30 | 2007-11-30 | Hitachi Ltd | A semiconductor device and a method of manufacturing the same |
JP2002026195A (ja) * | 2000-07-11 | 2002-01-25 | Fuji Electric Co Ltd | 樹脂封止型半導体装置及びその製造方法 |
JP3660861B2 (ja) * | 2000-08-18 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4669166B2 (ja) * | 2000-08-31 | 2011-04-13 | エルピーダメモリ株式会社 | 半導体装置 |
JP2002093982A (ja) * | 2000-09-13 | 2002-03-29 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP3709139B2 (ja) * | 2001-01-04 | 2005-10-19 | 吉川工業株式会社 | ノンリード・プラスチック半導体パッケージ構造 |
SG120858A1 (en) * | 2001-08-06 | 2006-04-26 | Micron Technology Inc | Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same |
JP2004103860A (ja) * | 2002-09-10 | 2004-04-02 | Fujitsu Ltd | 半導体装置、カメラモジュール及びその製造方法 |
US7315077B2 (en) * | 2003-11-13 | 2008-01-01 | Fairchild Korea Semiconductor, Ltd. | Molded leadless package having a partially exposed lead frame pad |
US7208818B2 (en) * | 2004-07-20 | 2007-04-24 | Alpha And Omega Semiconductor Ltd. | Power semiconductor package |
KR100673380B1 (ko) * | 2004-12-20 | 2007-01-24 | 삼성전자주식회사 | 냉매로가 형성된 반도체 칩과, 그를 이용한 반도체 패키지및 반도체 패키지 냉각 시스템 |
JP2008270661A (ja) * | 2007-04-24 | 2008-11-06 | Mitsui High Tec Inc | リードフレームおよびリードフレームの製造方法ならびに半導体装置および半導体装置の製造方法 |
JP5173654B2 (ja) | 2007-08-06 | 2013-04-03 | セイコーインスツル株式会社 | 半導体装置 |
JP2009076658A (ja) * | 2007-09-20 | 2009-04-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US20090091009A1 (en) * | 2007-10-03 | 2009-04-09 | Corisis David J | Stackable integrated circuit package |
US20130009300A1 (en) * | 2010-03-31 | 2013-01-10 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing same |
US9059151B2 (en) * | 2010-07-20 | 2015-06-16 | Stats Chippac Ltd. | Integrated circuit packaging system with island terminals and embedded paddle and method of manufacture thereof |
-
2013
- 2013-02-07 JP JP2013022649A patent/JP6092645B2/ja not_active Expired - Fee Related
-
2014
- 2014-01-21 TW TW103102116A patent/TWI588948B/zh not_active IP Right Cessation
- 2014-01-26 CN CN201410037891.8A patent/CN103985675B/zh not_active Expired - Fee Related
- 2014-02-04 US US14/172,247 patent/US9397026B2/en active Active
- 2014-02-06 KR KR1020140013452A patent/KR102145167B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP2014154689A (ja) | 2014-08-25 |
TWI588948B (zh) | 2017-06-21 |
CN103985675B (zh) | 2018-05-01 |
US20140217602A1 (en) | 2014-08-07 |
TW201442161A (zh) | 2014-11-01 |
KR102145167B1 (ko) | 2020-08-18 |
CN103985675A (zh) | 2014-08-13 |
KR20140100904A (ko) | 2014-08-18 |
US9397026B2 (en) | 2016-07-19 |
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