JP7484770B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP7484770B2 JP7484770B2 JP2021030287A JP2021030287A JP7484770B2 JP 7484770 B2 JP7484770 B2 JP 7484770B2 JP 2021030287 A JP2021030287 A JP 2021030287A JP 2021030287 A JP2021030287 A JP 2021030287A JP 7484770 B2 JP7484770 B2 JP 7484770B2
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- 239000004065 semiconductor Substances 0.000 title claims description 94
- 239000011810 insulating material Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 230000017525 heat dissipation Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/49548—Cross section geometry
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- H01L23/495—Lead-frames or other flat leads
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- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Condensed Matter Physics & Semiconductors (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
図1は、実施の形態1に係る半導体パッケージの内部を示す上面図である。図2,3は、実施の形態1に係る半導体パッケージを示す断面図である。図4は、実施の形態1に係る半導体パッケージを示す下面図である。図2は図1のI-IIに沿った断面図である。図3は図1のIII-IVに沿った断面図である。この半導体パッケージは6in1のIPM(Intelligent Power Module)である。
図5,6は、実施の形態2に係る半導体パッケージを示す断面図である。図5,6の断面はそれぞれ実施の形態1の図2,3の断面に対応する。本実施の形態では、絶縁材10がパッケージ7の下面に密着し、溝8に入り込んでいる。絶縁材10は、パッケージ7の材質よりも高い熱伝導率を持ち、例えばヤング率500[MPa]以下のウレタン等である。
図7は、実施の形態3に係る半導体パッケージの内部を示す上面図である。図8は、実施の形態3に係る半導体パッケージを示す断面図である。図8は図7のI-IIに沿った断面図である。本実施の形態では、シャント抵抗11がリード端子6a~6cの上に設けられている。シャント抵抗11の一端はリード端子6a~6cに接続され、他端はエミッタ端子(不図示)を介して接地されている。シャント抵抗11は、短絡保護のために電流を検出するのに用いられる。
図9,10は、実施の形態4に係る半導体パッケージを示す断面図である。図9,10の断面はそれぞれ実施の形態1の図2,3の断面に対応する。本実施の形態では、銅などからなる金属パターン12が絶縁材10の下面に設けられている。このように外装した金属パターン12からの放熱が可能になるため、ダイパッド3a~3d及びリード端子6a~6fの放熱性が更に向上する。その他の構成及び効果は実施の形態3と同様である。
図11,12は、実施の形態5に係る半導体パッケージを示す断面図である。図13は、実施の形態5に係る半導体パッケージを示す下面図である。図11,12の断面はそれぞれ実施の形態1の図2,3の断面に対応する。本実施の形態では、エポキシ樹脂などの樹脂13により絶縁材10を封止している。金属パターン12の下面は樹脂13から露出している。その他の構成は実施の形態4と同様である。
図14は、実施の形態6に係る半導体パッケージを示す断面図である。図15は、実施の形態6に係る半導体パッケージを示す下面図である。本実施の形態では、発熱量が小さい制御チップ4a,4bが設けられたリードフレーム5はパッケージ7の下面から露出していない。即ち、主な発熱源となる半導体チップ1a~1f,2a~2fが設けられたダイパッド3a~3dと複数のリード端子6a~6fのみをパッケージ7の下面から露出させている。その他の構成は実施の形態2と同様である。この場合でも実施の形態2と同様に放熱性を向上させることができる。
Claims (8)
- 複数のダイパッドと、
前記複数のダイパッドの上にそれぞれ設けられた複数の半導体チップと、
前記複数の半導体チップにそれぞれ接続された複数のリード端子と、
前記複数のダイパッド、前記複数の半導体チップ、及び前記複数のリード端子を封止したパッケージとを備え、
前記複数のダイパッドと前記複数のリード端子は前記パッケージの下面から露出し、
前記複数のダイパッドは、第1のダイパッドと第2のダイパッドを有し、
前記複数の半導体チップは、前記第1のダイパッドの上に設けられ前記第1のダイパッドに下面電極が接続された第1の半導体チップと、前記第2のダイパッドの上に設けられ前記第2のダイパッドに下面電極が接続された第2の半導体チップとを有し、
前記複数のリード端子は、前記第1のダイパッドと一体形成された第1のリード端子と、前記第2のダイパッドと一体形成された第2のリード端子と、前記第1の半導体チップの上面電極とワイヤ接続された第3のリード端子とを有し、
前記パッケージの前記下面には、隣接する前記第1のダイパッド及び前記第1のリード端子の組と前記第2のダイパッド及び前記第2のリード端子の組との間、及び、隣接する前記第1のダイパッド及び前記第1のリード端子の組と前記第3のリード端子との間に溝が設けられていることを特徴とする半導体パッケージ。 - 前記複数のダイパッドと前記複数のリード端子は前記パッケージの下面において面一になっていることを特徴とする請求項1に記載の半導体パッケージ。
- 前記パッケージの前記下面に密着し、前記溝に入り込み、前記パッケージよりも高い熱伝導率を持つ絶縁材を更に備えることを特徴とする請求項1又は2に記載の半導体パッケージ。
- 前記複数のリード端子は、前記第2の半導体チップの上面電極とワイヤ接続された第4のリード端子を更に有し、
隣接する前記第3のリード端子及び前記第4のリード端子に一端が接続され、他端が接地されたシャント抵抗を更に備えることを特徴とする請求項1~3の何れか1項に記載の半導体パッケージ。 - 前記絶縁材の下面に設けられた金属パターンを更に備えることを特徴とする請求項3に記載の半導体パッケージ。
- 前記絶縁材を封止する樹脂を更に備えることを特徴とする請求項3又は5に記載の半導体パッケージ。
- リードフレームと、
前記リードフレームの上に設けられ、前記複数の半導体チップを制御する制御チップとを更に備え、
前記リードフレームは前記パッケージの下面から露出していないことを特徴とする請求項1~6の何れか1項に記載の半導体パッケージ。 - 前記複数の半導体チップはワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1~7の何れか1項に記載の半導体パッケージ。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021030287A JP7484770B2 (ja) | 2021-02-26 | 2021-02-26 | 半導体パッケージ |
US17/403,135 US11798869B2 (en) | 2021-02-26 | 2021-08-16 | Semiconductor package with plurality of grooves on lower surface |
DE102021128793.6A DE102021128793A1 (de) | 2021-02-26 | 2021-11-05 | Halbleitergehäuse |
CN202210157788.1A CN114975335A (zh) | 2021-02-26 | 2022-02-21 | 半导体封装件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021030287A JP7484770B2 (ja) | 2021-02-26 | 2021-02-26 | 半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
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JP2022131370A JP2022131370A (ja) | 2022-09-07 |
JP7484770B2 true JP7484770B2 (ja) | 2024-05-16 |
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Application Number | Title | Priority Date | Filing Date |
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JP2021030287A Active JP7484770B2 (ja) | 2021-02-26 | 2021-02-26 | 半導体パッケージ |
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US (1) | US11798869B2 (ja) |
JP (1) | JP7484770B2 (ja) |
CN (1) | CN114975335A (ja) |
DE (1) | DE102021128793A1 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004208411A (ja) | 2002-12-25 | 2004-07-22 | Denso Corp | ハーフブリッジ回路用半導体モジュール |
JP2009302526A (ja) | 2008-05-16 | 2009-12-24 | Denso Corp | 電子回路装置及びその製造方法 |
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US6818973B1 (en) * | 2002-09-09 | 2004-11-16 | Amkor Technology, Inc. | Exposed lead QFP package fabricated through the use of a partial saw process |
US8067821B1 (en) * | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
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US8575742B1 (en) * | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
JP5876669B2 (ja) * | 2010-08-09 | 2016-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6092645B2 (ja) * | 2013-02-07 | 2017-03-08 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
KR101963271B1 (ko) * | 2014-01-28 | 2019-07-31 | 삼성전기주식회사 | 파워모듈 패키지 및 그 제조방법 |
JP2021030287A (ja) | 2019-08-28 | 2021-03-01 | 日立金属株式会社 | 非晶質合金薄帯の加工装置、及び、非晶質合金薄帯の加工方法 |
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JP2004208411A (ja) | 2002-12-25 | 2004-07-22 | Denso Corp | ハーフブリッジ回路用半導体モジュール |
JP2009302526A (ja) | 2008-05-16 | 2009-12-24 | Denso Corp | 電子回路装置及びその製造方法 |
US20120061819A1 (en) | 2010-09-13 | 2012-03-15 | Ralf Siemieniec | Semiconductor Module and Method for Production Thereof |
JP2015106685A (ja) | 2013-12-02 | 2015-06-08 | 三菱電機株式会社 | パワーモジュール及びその製造方法 |
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