CN103985675A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN103985675A CN103985675A CN201410037891.8A CN201410037891A CN103985675A CN 103985675 A CN103985675 A CN 103985675A CN 201410037891 A CN201410037891 A CN 201410037891A CN 103985675 A CN103985675 A CN 103985675A
- Authority
- CN
- China
- Prior art keywords
- pin
- semiconductor device
- island
- recess
- insulative resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013022649A JP6092645B2 (ja) | 2013-02-07 | 2013-02-07 | 半導体装置 |
JP2013-022649 | 2013-02-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103985675A true CN103985675A (zh) | 2014-08-13 |
CN103985675B CN103985675B (zh) | 2018-05-01 |
Family
ID=51258611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410037891.8A Expired - Fee Related CN103985675B (zh) | 2013-02-07 | 2014-01-26 | 半导体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9397026B2 (zh) |
JP (1) | JP6092645B2 (zh) |
KR (1) | KR102145167B1 (zh) |
CN (1) | CN103985675B (zh) |
TW (1) | TWI588948B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ITTO20120854A1 (it) * | 2012-09-28 | 2014-03-29 | Stmicroelectronics Malta Ltd | Contenitore a montaggio superficiale perfezionato per un dispositivo integrato a semiconduttori, relativo assemblaggio e procedimento di fabbricazione |
JP6357371B2 (ja) * | 2014-07-09 | 2018-07-11 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
JP6494465B2 (ja) * | 2015-08-03 | 2019-04-03 | エイブリック株式会社 | 半導体装置の製造方法 |
JP7484770B2 (ja) * | 2021-02-26 | 2024-05-16 | 三菱電機株式会社 | 半導体パッケージ |
JP2023036447A (ja) * | 2021-09-02 | 2023-03-14 | 新電元工業株式会社 | リードフレーム一体型基板、半導体装置、リードフレーム一体型基板の製造方法、及び半導体装置の製造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5886404A (en) * | 1996-06-18 | 1999-03-23 | Lg Semicon Co., Ltd. | Bottom lead semiconductor package having folded leads |
JP2000332162A (ja) * | 1999-05-18 | 2000-11-30 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
JP2002203936A (ja) * | 2001-01-04 | 2002-07-19 | Yoshikawa Kogyo Co Ltd | ノンリード・プラスチック半導体パッケージ構造 |
JP2008270661A (ja) * | 2007-04-24 | 2008-11-06 | Mitsui High Tec Inc | リードフレームおよびリードフレームの製造方法ならびに半導体装置および半導体装置の製造方法 |
CN101393900A (zh) * | 2007-09-20 | 2009-03-25 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
US20120018865A1 (en) * | 2010-07-20 | 2012-01-26 | Zigmund Ramirez Camacho | Integrated circuit packaging system with island terminals and embedded paddle and method of manufacture thereof |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4827611A (en) * | 1988-03-28 | 1989-05-09 | Control Data Corporation | Compliant S-leads for chip carriers |
JP2521518B2 (ja) * | 1988-06-30 | 1996-08-07 | 松下電子工業株式会社 | 半導体集積回路パッケ―ジ |
KR930024126A (ko) * | 1992-05-12 | 1993-12-22 | 아키라 기타하라 | 표면실장소자와 그의 반제품 |
US5286999A (en) * | 1992-09-08 | 1994-02-15 | Texas Instruments Incorporated | Folded bus bar leadframe |
US5604376A (en) * | 1994-06-30 | 1997-02-18 | Digital Equipment Corporation | Paddleless molded plastic semiconductor chip package |
US6211462B1 (en) * | 1998-11-05 | 2001-04-03 | Texas Instruments Incorporated | Low inductance power package for integrated circuits |
JP2000299400A (ja) | 1999-04-14 | 2000-10-24 | Sony Corp | ノンリード・フラットパッケージ型半導体装置 |
MY133357A (en) * | 1999-06-30 | 2007-11-30 | Hitachi Ltd | A semiconductor device and a method of manufacturing the same |
JP2002026195A (ja) * | 2000-07-11 | 2002-01-25 | Fuji Electric Co Ltd | 樹脂封止型半導体装置及びその製造方法 |
JP3660861B2 (ja) * | 2000-08-18 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4669166B2 (ja) * | 2000-08-31 | 2011-04-13 | エルピーダメモリ株式会社 | 半導体装置 |
JP2002093982A (ja) * | 2000-09-13 | 2002-03-29 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
SG120858A1 (en) * | 2001-08-06 | 2006-04-26 | Micron Technology Inc | Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same |
JP2004103860A (ja) * | 2002-09-10 | 2004-04-02 | Fujitsu Ltd | 半導体装置、カメラモジュール及びその製造方法 |
US7315077B2 (en) * | 2003-11-13 | 2008-01-01 | Fairchild Korea Semiconductor, Ltd. | Molded leadless package having a partially exposed lead frame pad |
US7208818B2 (en) * | 2004-07-20 | 2007-04-24 | Alpha And Omega Semiconductor Ltd. | Power semiconductor package |
KR100673380B1 (ko) * | 2004-12-20 | 2007-01-24 | 삼성전자주식회사 | 냉매로가 형성된 반도체 칩과, 그를 이용한 반도체 패키지및 반도체 패키지 냉각 시스템 |
JP5173654B2 (ja) | 2007-08-06 | 2013-04-03 | セイコーインスツル株式会社 | 半導体装置 |
US20090091009A1 (en) * | 2007-10-03 | 2009-04-09 | Corisis David J | Stackable integrated circuit package |
JPWO2011121756A1 (ja) * | 2010-03-31 | 2013-07-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
-
2013
- 2013-02-07 JP JP2013022649A patent/JP6092645B2/ja not_active Expired - Fee Related
-
2014
- 2014-01-21 TW TW103102116A patent/TWI588948B/zh not_active IP Right Cessation
- 2014-01-26 CN CN201410037891.8A patent/CN103985675B/zh not_active Expired - Fee Related
- 2014-02-04 US US14/172,247 patent/US9397026B2/en active Active
- 2014-02-06 KR KR1020140013452A patent/KR102145167B1/ko active IP Right Grant
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5886404A (en) * | 1996-06-18 | 1999-03-23 | Lg Semicon Co., Ltd. | Bottom lead semiconductor package having folded leads |
JP2000332162A (ja) * | 1999-05-18 | 2000-11-30 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
JP2002203936A (ja) * | 2001-01-04 | 2002-07-19 | Yoshikawa Kogyo Co Ltd | ノンリード・プラスチック半導体パッケージ構造 |
JP2008270661A (ja) * | 2007-04-24 | 2008-11-06 | Mitsui High Tec Inc | リードフレームおよびリードフレームの製造方法ならびに半導体装置および半導体装置の製造方法 |
CN101393900A (zh) * | 2007-09-20 | 2009-03-25 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
US20120018865A1 (en) * | 2010-07-20 | 2012-01-26 | Zigmund Ramirez Camacho | Integrated circuit packaging system with island terminals and embedded paddle and method of manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
US9397026B2 (en) | 2016-07-19 |
US20140217602A1 (en) | 2014-08-07 |
TW201442161A (zh) | 2014-11-01 |
TWI588948B (zh) | 2017-06-21 |
KR102145167B1 (ko) | 2020-08-18 |
JP6092645B2 (ja) | 2017-03-08 |
KR20140100904A (ko) | 2014-08-18 |
JP2014154689A (ja) | 2014-08-25 |
CN103985675B (zh) | 2018-05-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20160330 Address after: Chiba County, Japan Applicant after: DynaFine Semiconductor Co.,Ltd. Address before: Chiba County, Japan Applicant before: Seiko Instruments Inc. |
|
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: Chiba County, Japan Applicant after: ABLIC Inc. Address before: Chiba County, Japan Applicant before: DynaFine Semiconductor Co.,Ltd. |
|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180501 Termination date: 20220126 |