JP5592053B2 - 半導体装置及びその製造方法 - Google Patents
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Description
11 半導体チップ
11A 半導体基板
12 保護膜
14,71,73 絶縁膜
15,16 貫通電極
15A,16A 貫通部
17A,17B 再配線
18 封止樹脂
20,21 ポスト
22 ソルダーレジスト
25 外部接続端子
28 グランド層
30 無機絶縁層
31 絶縁層
33 パッチアンテナ
35 基板本体
35A 第1面
35B 第2面
36 素子形成層
37 電極パッド
39A,39B 貫通孔
41 ビア部
42 アンテナ部
45,46,48,49,50 レジスト層
61 逆F型アンテナ
62 ダイポールアンテナ
B 半導体装置形成領域
D 切断位置
Claims (8)
- 半導体チップと、該半導体チップを貫通して形成された貫通電極とを有した半導体装置であって、
前記半導体チップは、主面に素子形成層が形成された半導体基板を含み、
前記半導体チップを貫通して設けられた貫通孔と、
前記貫通孔の内壁から、前記半導体基板の主面に対する反対側面上にかけて設けられた絶縁膜と、
前記貫通孔内に前記絶縁膜を介して設けられた前記貫通電極と、
前記反対側面上に前記絶縁膜のみを介して設けられたグランド層と、
前記グランド層上に設けられたSiO 2 又はSiNである無機絶縁層と、
前記グランド層上に前記無機絶縁層を介して設けられ、前記貫通電極に接続されたアンテナと、を有し、
前記無機絶縁層上に設けられた前記アンテナが、前記無機絶縁層内に設けられたビアを介して前記貫通電極に接続され、
前記貫通電極が、前記アンテナに接続された第1の貫通電極と、前記グランド層に接続された第2の貫通電極とを有し、
前記グランド層と、前記第2の貫通電極とが一体に形成されている半導体装置。 - 前記無機絶縁層の厚さが1〜3μmである請求項1に記載の半導体装置。
- 前記アンテナは、パッチアンテナ、逆F型アンテナ、及びダイポールアンテナの群から選ばれる少なくともひとつのアンテナである請求項1または2に記載の半導体装置。
- 前記半導体基板の主面上に再配線が形成されてなり、
前記再配線は前記貫通電極に接続され、
前記再配線には外部接続端子が設けられている請求項1乃至3のいずれか一項に記載の半導体装置。 - 主面に素子形成層が形成された半導体基板に貫通孔を形成する工程と、
前記貫通孔の内壁から、前記半導体基板の主面に対する反対側面上にかけて絶縁膜を形成する工程と、
前記貫通孔内に前記絶縁膜を介して貫通電極を形成する工程と、
前記反対側面上に前記絶縁膜のみを介してグランド層を形成する工程と、
前記グランド層上にSiO 2 又はSiNである無機絶縁層を形成する工程と、
前記グランド層上に、前記無機絶縁層を介して形成され、前記貫通電極に接続されたアンテナを形成する工程と、
前記半導体基板を切断して個片化し、半導体装置を形成する工程とを含み、
前記無機絶縁層上に設けられた前記アンテナが、前記無機絶縁層内に設けられたビアを介して前記貫通電極に接続され、
前記貫通電極が、前記アンテナに接続された第1の貫通電極と、前記グランド層に接続された第2の貫通電極とを有し、
前記グランド層と、前記第2の貫通電極とが一体に形成されている半導体装置の製造方法。 - 前記無機絶縁層の厚さが1〜3μmである請求項5に記載の半導体装置の製造方法。
- 前記アンテナは、パッチアンテナ、逆F型アンテナ、及びダイポールアンテナの群から選ばれる少なくともひとつのアンテナである請求項5または6に記載の半導体装置の製造方法。
- 前記半導体基板の主面上に、前記貫通電極と電気的に接続される再配線を形成する工程と、
前記再配線に外部接続端子を形成する工程を更に有する請求項5乃至7のいずれか一項に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007335690A JP5592053B2 (ja) | 2007-12-27 | 2007-12-27 | 半導体装置及びその製造方法 |
US12/342,755 US8035192B2 (en) | 2007-12-27 | 2008-12-23 | Semiconductor device and manufacturing method thereof |
KR1020080134561A KR20090071482A (ko) | 2007-12-27 | 2008-12-26 | 반도체 장치 및 그 제조 방법 |
TW097150906A TW200931623A (en) | 2007-12-27 | 2008-12-26 | Semiconductor device and manufacturing method thereof |
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JP2007335690A JP5592053B2 (ja) | 2007-12-27 | 2007-12-27 | 半導体装置及びその製造方法 |
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JP2009158743A JP2009158743A (ja) | 2009-07-16 |
JP2009158743A5 JP2009158743A5 (ja) | 2011-01-06 |
JP5592053B2 true JP5592053B2 (ja) | 2014-09-17 |
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JP (1) | JP5592053B2 (ja) |
KR (1) | KR20090071482A (ja) |
TW (1) | TW200931623A (ja) |
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WO2009136495A1 (ja) * | 2008-05-09 | 2009-11-12 | 国立大学法人九州工業大学 | チップサイズ両面接続パッケージ及びその製造方法 |
US8896136B2 (en) * | 2010-06-30 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment mark and method of formation |
US20120306094A1 (en) * | 2011-06-06 | 2012-12-06 | Shahrazie Zainal Abu Bakar | Signal routing using through-substrate vias |
EP2648218B1 (en) | 2012-04-05 | 2015-10-14 | Nxp B.V. | Integrated circuit and method of manufacturing the same |
US9166284B2 (en) * | 2012-12-20 | 2015-10-20 | Intel Corporation | Package structures including discrete antennas assembled on a device |
TWI544593B (zh) * | 2013-09-09 | 2016-08-01 | 矽品精密工業股份有限公司 | 半導體裝置及其製法 |
JP6869649B2 (ja) | 2016-06-13 | 2021-05-12 | ラピスセミコンダクタ株式会社 | 半導体装置、通信システムおよび半導体装置の製造方法。 |
CN108235792B (zh) * | 2016-10-21 | 2021-01-26 | 京瓷株式会社 | 标签用基板、rfid标签以及rfid*** |
KR102334710B1 (ko) | 2017-03-28 | 2021-12-02 | 삼성전기주식회사 | 전자부품 내장 기판 |
US10181447B2 (en) | 2017-04-21 | 2019-01-15 | Invensas Corporation | 3D-interconnect |
CN109411535B (zh) * | 2017-08-15 | 2022-03-18 | 台达电子工业股份有限公司 | 半导体装置 |
KR102019354B1 (ko) * | 2017-11-03 | 2019-09-09 | 삼성전자주식회사 | 안테나 모듈 |
KR20200099805A (ko) | 2019-02-15 | 2020-08-25 | 삼성전자주식회사 | 반도체 패키지 |
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JP4010881B2 (ja) | 2002-06-13 | 2007-11-21 | 新光電気工業株式会社 | 半導体モジュール構造 |
JP4290158B2 (ja) * | 2004-12-20 | 2009-07-01 | 三洋電機株式会社 | 半導体装置 |
JP2007049115A (ja) * | 2005-07-13 | 2007-02-22 | Seiko Epson Corp | 半導体装置 |
JP2007036571A (ja) * | 2005-07-26 | 2007-02-08 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US7531407B2 (en) * | 2006-07-18 | 2009-05-12 | International Business Machines Corporation | Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same |
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US8035192B2 (en) | 2011-10-11 |
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US20090166811A1 (en) | 2009-07-02 |
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