JP5054413B2 - アンテナ素子及び半導体装置 - Google Patents
アンテナ素子及び半導体装置 Download PDFInfo
- Publication number
- JP5054413B2 JP5054413B2 JP2007102501A JP2007102501A JP5054413B2 JP 5054413 B2 JP5054413 B2 JP 5054413B2 JP 2007102501 A JP2007102501 A JP 2007102501A JP 2007102501 A JP2007102501 A JP 2007102501A JP 5054413 B2 JP5054413 B2 JP 5054413B2
- Authority
- JP
- Japan
- Prior art keywords
- antenna
- silicon substrate
- layer
- signal input
- electromagnetic wave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/24—Supports; Mounting means by structural association with other equipment or articles with receiving set
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Details Of Aerials (AREA)
- Transceivers (AREA)
- Waveguide Aerials (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
Description
図3は、本発明の第1の実施の形態に係る半導体装置の断面図である。
図7は、本発明の第2の実施の形態に係る半導体装置の断面図である。図7において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
図11は、本発明の第3の実施の形態に係る半導体装置の断面図である。図11において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
図15は、本発明の第4の実施の形態に係る半導体装置の断面図である。図15において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
11,91,121 配線基板
12 CPU用半導体チップ
13 RFデバイス
15,75,95,125 アンテナ素子
17 基板本体
21〜27,93,94,131〜135 配線
31,76,96,138 シリコン基板
17A,31A,76A,96A,138A 上面
31B,76B,96B,138B 下面
32 絶縁膜
33 逆F型アンテナ
35,41 Ni層
36,42 Au層
37,43,99,143 ソルダーレジスト
43A〜43E,97A〜97C,143A〜143F 開口部
45〜49,102〜104 外部接続端子
52,53,106,152,153 貫通孔
56,57,107,157,158 接続部
58,109,161,162 信号入力用パッド
59,77,111,163 グラウンド層
62,112,165,166 電磁波送受信部
77 逆L型アンテナ
81,115,169 溝部
97 パッチアンテナ
141 ダイポールアンテナ
M1〜M3 厚さ
W1〜W14 幅
Claims (3)
- 電磁波の送受信を行う電磁波送受信部と、信号入力用パッドと、グラウンド層と、前記電磁波送受信部と前記信号入力用パッドとを電気的に接続する接続部とを有したアンテナを備えたアンテナ素子であって、
前記アンテナが形成されるシリコン基板と、前記シリコン基板と前記アンテナとを電気的に絶縁する絶縁膜とを設け、
前記シリコン基板の第1の面に、前記絶縁膜を介して、前記電磁波送受信部を配置すると共に、前記第1の面とは反対側に位置する前記シリコン基板の第2の面に、前記絶縁膜を介して、前記グラウンド層及び前記信号入力用パッドを配置し、
前記グラウンド層と前記信号入力用パッドとは、前記第2の面上で電気的に接続され、
前記シリコン基板を貫通するように前記接続部を配置し、
前記電磁波送受信部、前記信号入力用パッド、及び前記グラウンド層は、外部接続端子が形成される部分を除いてソルダーレジストに覆われていることを特徴とするアンテナ素子。 - 前記アンテナは、めっき膜により構成することを特徴とする請求項1記載のアンテナ素子。
- 請求項1又は2記載のアンテナ素子と、
前記アンテナ素子と電気的に接続される電子部品と、
前記アンテナ素子及び前記電子部品が実装される配線基板と、を備えたことを特徴とする半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007102501A JP5054413B2 (ja) | 2007-04-10 | 2007-04-10 | アンテナ素子及び半導体装置 |
KR1020080032754A KR20080092278A (ko) | 2007-04-10 | 2008-04-08 | 안테나 소자 및 반도체 장치 |
US12/099,983 US8018392B2 (en) | 2007-04-10 | 2008-04-09 | Antenna element and semiconductor device |
TW097112859A TW200847386A (en) | 2007-04-10 | 2008-04-09 | Antenna element and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007102501A JP5054413B2 (ja) | 2007-04-10 | 2007-04-10 | アンテナ素子及び半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008263263A JP2008263263A (ja) | 2008-10-30 |
JP2008263263A5 JP2008263263A5 (ja) | 2010-04-08 |
JP5054413B2 true JP5054413B2 (ja) | 2012-10-24 |
Family
ID=39985455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007102501A Active JP5054413B2 (ja) | 2007-04-10 | 2007-04-10 | アンテナ素子及び半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8018392B2 (ja) |
JP (1) | JP5054413B2 (ja) |
KR (1) | KR20080092278A (ja) |
TW (1) | TW200847386A (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10373508B2 (en) * | 2012-06-27 | 2019-08-06 | Intel Corporation | Devices, systems, and methods for enriching communications |
JP2014170811A (ja) * | 2013-03-01 | 2014-09-18 | Sony Corp | CSP(ChipSizePackage) |
US20150325534A1 (en) * | 2014-05-09 | 2015-11-12 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package for radio communication and method of manufacturing the same |
WO2016130090A1 (en) * | 2015-02-13 | 2016-08-18 | Nanyang Technological University | Semiconductor arrangement and method for fabricating thereof |
USD926716S1 (en) * | 2019-07-31 | 2021-08-03 | Eryn Smith | Antenna pattern for a semiconductive substrate carrier |
USD913256S1 (en) * | 2019-07-31 | 2021-03-16 | Eryn Smith | Antenna pattern for a semiconductive substrate carrier |
KR20220066536A (ko) | 2020-11-16 | 2022-05-24 | 삼성전기주식회사 | 안테나 장치 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3196451B2 (ja) * | 1993-10-28 | 2001-08-06 | 株式会社村田製作所 | マイクロストリップアンテナ |
JP3417729B2 (ja) * | 1995-06-09 | 2003-06-16 | 東光株式会社 | 平面アンテナ |
JP3313045B2 (ja) * | 1997-04-17 | 2002-08-12 | 松下電器産業株式会社 | 半導体装置 |
JP4183218B2 (ja) | 1999-10-18 | 2008-11-19 | Tdk株式会社 | チップアンテナの製造方法 |
JP4010881B2 (ja) * | 2002-06-13 | 2007-11-21 | 新光電気工業株式会社 | 半導体モジュール構造 |
JP2004327568A (ja) * | 2003-04-23 | 2004-11-18 | Japan Science & Technology Agency | 半導体装置 |
US7742000B2 (en) * | 2005-05-31 | 2010-06-22 | Tialinx, Inc. | Control of an integrated beamforming array using near-field-coupled or far-field-coupled commands |
JP4749795B2 (ja) * | 2005-08-05 | 2011-08-17 | 新光電気工業株式会社 | 半導体装置 |
JP4876491B2 (ja) * | 2005-09-02 | 2012-02-15 | 株式会社村田製作所 | 誘電体アンテナ |
US7724109B2 (en) * | 2005-11-17 | 2010-05-25 | Cts Corporation | Ball grid array filter |
EP2002508A1 (en) * | 2006-03-17 | 2008-12-17 | Nxp B.V. | Antenna device and rf communication equipment |
CN101401114B (zh) * | 2006-04-03 | 2011-03-16 | 松下电器产业株式会社 | 天线内置半导体存储模块 |
-
2007
- 2007-04-10 JP JP2007102501A patent/JP5054413B2/ja active Active
-
2008
- 2008-04-08 KR KR1020080032754A patent/KR20080092278A/ko not_active Application Discontinuation
- 2008-04-09 US US12/099,983 patent/US8018392B2/en active Active
- 2008-04-09 TW TW097112859A patent/TW200847386A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
JP2008263263A (ja) | 2008-10-30 |
US8018392B2 (en) | 2011-09-13 |
US20090009402A1 (en) | 2009-01-08 |
KR20080092278A (ko) | 2008-10-15 |
TW200847386A (en) | 2008-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5054413B2 (ja) | アンテナ素子及び半導体装置 | |
JP5592053B2 (ja) | 半導体装置及びその製造方法 | |
KR101436037B1 (ko) | 인덕터 소자 및 그 제조 방법 | |
US7851918B2 (en) | Three-dimensional package module | |
JP5669043B2 (ja) | ポスト壁導波路アンテナ及びアンテナモジュール | |
US12015204B2 (en) | Semiconductor device, communication system, and method of manufacturing semiconductor device | |
KR20040067932A (ko) | 전자장치 및 안테나 실장 인쇄회로기판 | |
CN110890331A (zh) | 半导体装置封装及其制造方法 | |
CN112310611A (zh) | 片式天线 | |
JPWO2020009037A1 (ja) | アンテナモジュール及び通信装置 | |
US6643924B2 (en) | Method of manufacturing a distributed constant filter circuit module | |
JP4479606B2 (ja) | アンテナ装置 | |
JP2004236327A (ja) | 接地導体板を組込んだマルチセグメント型平面アンテナ | |
JP2002135041A (ja) | パッチアンテナおよびそれを含むrfユニット | |
JP2007036315A (ja) | 高周波電子部品 | |
CN110098480B (zh) | 片式天线及包括该片式天线的天线模块 | |
JP6807946B2 (ja) | アンテナ、モジュール基板およびモジュール | |
CN110911826A (zh) | 片式天线模块 | |
CN109792104B (zh) | 天线装置、天线组装件和通信装置 | |
US9755313B2 (en) | Chip antenna for near field communication and method of manufacturing the same | |
CN114512801A (zh) | 天线装置 | |
JP6761480B2 (ja) | アンテナ、モジュール基板およびモジュール | |
TW201721966A (zh) | 晶片訊號元件之製作方法 | |
JP2001088097A (ja) | ミリ波多層基板モジュール及びその製造方法 | |
US11011846B2 (en) | Antenna and semiconductor device with improved tradeoff relationship between antenna gain and antenna size |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100218 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100218 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110811 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110823 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111021 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120214 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120410 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120717 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120727 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5054413 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150803 Year of fee payment: 3 |