JP5579629B2 - プログラマブルロジックデバイス回路に結合されるクロックデータリカバリ回路 - Google Patents
プログラマブルロジックデバイス回路に結合されるクロックデータリカバリ回路 Download PDFInfo
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
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- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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Description
REFCLK*W=EMBCLK
ここでWは0.5,1,2,4等の適宜なスケールファクタとすることができる。要素22と30の間の点線はこれらの要素の出力の間に周波数相関性があることを示しており、従ってソース22によって形成される基準クロック信号の周波数(またはこの信号の任意の分数あるいは整数倍の周波数)がCDRデータ信号の周波数を確立するために要素30によって使用され得る。しかしながら、要素20と30の出力信号の間に特定の位相関係が存在する必要はない。
前述した説明から、(D信号を使用して選択される、可能ないくつかの周波数レンジいずれかの範囲において)クロック信号の周波数はVCO電流制御信号を変化させることによって上昇または低下させることができることが理解される。ドライバ132の閉ループを通じた真または補のパスは、全体としてクロック信号周期を8つの等時間インタバルに有効に分割する8つの点においてタップされる。これらの8つの点における信号は、前述した8つの等間隔で位相シフトされたクロック信号として出力される。
REFCLK*W=EMBCLK
ここでWは0.5,1,2,4等の適宜なスケールファクタとすることができる。この基準クロック信号は図1に関連して記述したようにトランスミッタ320に伝送される。トランスミッタ320内のPLL100は図2に関連して記述したようにこの信号を処理し、所要のCDRクロック周波数に正確に等しい周波数を有する出力信号を形成する。この信号は図2の出力と同様に8個のクロック信号のうち1つとすることができ、これはこの信号の位相が重要ではないからである。(以下により詳細に記述するように、一般的なCDR信号レシーバ350は位相多様型であり、従って特定の位相を有する受信CDR信号に束縛されることはない。)
ク信号パルスに応答してロジック0を出力する状態に回帰する。充分短い時間のうちに立ち上がりエッジが後続していない立ち下がりエッジがリタイムされたデータ信号内に存在することに対して、回路600は一般的に同様な方式で応答する。しかしながら、リタイムされたデータ信号内の立ち下がりおよび立ち上がりエッジが時間的に充分接近している場合、カウンタ622は充分に頻繁にリセットされ、従って閾値カウントには決して到達せずRLVフラグ信号516は形成されない。
分なものとなる。このことによってレジスタ722aの出力信号をロジック0にすることができ、一方レジスタ712aの出力信号はロジック1となる。これによって再びXORゲート730aの出力信号がロジック1にされロック喪失問題を示すことができる。
Lをオンボードに備えていないがチップ820が最高周波数のクロック信号(例えばチップ810からの)を処理する必要がある図11Aの実施例とは対照的である。
ナリングが使用されることが少なくとも示唆されている。図11Aおよび図11Bの場合と同様に、図11Cに示された種々の要素の間の相互接続は一般的に図10に示されているものと同様である。
Claims (20)
- CDR信号を処理するための方法であって、該方法は、
データ情報と、シリアルデータ流の中に埋め込まれたクロック信号とを含むCDR信号を受信することと、
該CDR信号と同じソースから、該埋め込まれたクロック信号の周波数に関連する周波数を有する基準クロック信号を受信することと、
該埋め込まれたクロック信号の周波数と等しい周波数を有する該基準クロック信号から、復元されたクロック信号を生成することと、
該復元されたクロック信号の位相が実質的に該埋め込まれたクロック信号の位相と等しくなるまで該復元されたクロック信号の位相を調整することと、
該復元されたクロック信号を用いて、該CDR信号から該データ情報を復元することと
を含む、方法。 - 前記基準クロック信号の周波数は、プログラム可能なスケールファクタによって、前記埋め込まれたクロック信号の周波数に関連する、請求項1に記載の方法。
- 前記プログラム可能なスケールファクタは、遠隔ソースから受信される、請求項2に記載の方法。
- 内部クロック信号を生成することをさらに含み、前記基準クロック信号、前記復元されたクロック信号、該内部クロック信号の各々は、異なる周波数を有する、請求項1に記載の方法。
- 前記復元されたクロック信号と関連付けられるクロックレジームと、前記内部クロック信号と関連付けられるクロックレジームとの間に前記データ情報をバッファリングすることをさらに含む、請求項4に記載の方法。
- CDR信号を処理するための方法であって、該方法は、
CDR信号と同じソースから基準クロック信号を受信することと、
CDR信号ソースから、データ情報と、シリアルデータ流の中に埋め込まれたクロック信号とを含む該CDR信号を受信することであって、該埋め込まれたクロック信号は、該基準クロック信号の周波数に関連する周波数を有する、ことと、
該埋め込まれたクロック信号の周波数と等しい周波数を有する該基準クロック信号から、復元されたクロック信号を生成することと、
該復元されたクロック信号の位相が実質的に該埋め込まれたクロック信号の位相と等しくなるまで該復元されたクロック信号の位相を調整することと、
該復元されたクロック信号を用いて、該CDR信号から該データ情報を復元することと
を含む、方法。 - 前記基準クロック信号の周波数は、プログラム可能なスケールファクタによって、前記埋め込まれたクロック信号の周波数に関連する、請求項6に記載の方法。
- 前記プログラム可能なスケールファクタは、遠隔ソースから受信される、請求項7に記載の方法。
- 内部クロック信号を生成することをさらに含み、前記基準クロック信号、前記復元されたクロック信号、該内部クロック信号の各々は、異なる周波数を有する、請求項6に記載の方法。
- 前記復元されたクロック信号と関連付けられるクロックレジームと、前記内部クロック信号と関連付けられるクロックレジームとの間に前記データ情報をバッファリングすることをさらに含む、請求項9に記載の方法。
- CDR信号を処理するための方法であって、該方法は、
データ情報信号を受信することと、
基準クロック信号を生成することと、
該基準クロック信号の周波数に関連する周波数を有する埋め込まれたクロック信号を生成することと、
該データ情報信号と、シリアルデータ流の中に埋め込まれた該埋め込まれたクロック信号とを含むCDR信号を生成することと、
該CDR信号および該基準クロック信号をCDR信号レシーバに伝送することと
を含む、方法。 - 前記基準クロック信号の周波数は、プログラム可能なスケールファクタによって、前記埋め込まれたクロック信号の周波数に関連する、請求項11に記載の方法。
- 前記プログラム可能なスケールファクタは、遠隔ソースから受信される、請求項12に記載の方法。
- 内部クロック信号を生成することをさらに含み、前記基準クロック信号、前記埋め込まれたクロック信号、該内部クロック信号の各々は、異なる周波数を有する、請求項11に記載の方法。
- 前記内部クロック信号と関連付けられるクロックレジームと、前記埋め込まれたクロック信号と関連付けられるクロックレジームとの間に前記データ情報をバッファリングすることをさらに含む、請求項14に記載の方法。
- CDR信号を処理するための方法であって、該方法は、
データ情報信号を受信することと、
基準クロック信号の周波数に関連する周波数を有する埋め込まれたクロック信号を生成することと、
該データ情報信号と、シリアルデータ流の中に埋め込まれた該埋め込まれたクロック信号とを含むCDR信号を生成することと、
該CDR信号および該基準クロック信号を該CDR信号レシーバに伝送することと
を含む、方法。 - 前記基準クロック信号の周波数は、プログラム可能なスケールファクタによって、前記埋め込まれたクロック信号の周波数に関連する、請求項16に記載の方法。
- 前記プログラム可能なスケールファクタは、遠隔ソースから受信される、請求項17に記載の方法。
- 内部クロック信号を生成することをさらに含み、前記基準クロック信号、前記埋め込まれたクロック信号、該内部クロック信号の各々は、異なる周波数を有する、請求項16に記載の方法。
- 前記内部クロック信号と関連付けられるクロックレジームと、前記埋め込まれたクロック信号と関連付けられるクロックレジームとの間に前記データ情報をバッファリングすることをさらに含む、請求項19に記載の方法。
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EP2056516B1 (en) | 2011-04-27 |
WO2001069837A2 (en) | 2001-09-20 |
JP2003527034A (ja) | 2003-09-09 |
EP2056516A1 (en) | 2009-05-06 |
JP2006262513A (ja) | 2006-09-28 |
JP3990570B2 (ja) | 2007-10-17 |
JP2011142631A (ja) | 2011-07-21 |
US20080031385A1 (en) | 2008-02-07 |
AU2001245715A1 (en) | 2001-09-24 |
JP4705604B2 (ja) | 2011-06-22 |
US7227918B2 (en) | 2007-06-05 |
JP2010172014A (ja) | 2010-08-05 |
DE60144544D1 (de) | 2011-06-09 |
JP2007195254A (ja) | 2007-08-02 |
JP2013179659A (ja) | 2013-09-09 |
JP4113898B2 (ja) | 2008-07-09 |
JP5933899B2 (ja) | 2016-06-15 |
US20010033188A1 (en) | 2001-10-25 |
US7684532B2 (en) | 2010-03-23 |
WO2001069837A3 (en) | 2003-01-03 |
EP1287633B1 (en) | 2009-01-07 |
EP1287633A2 (en) | 2003-03-05 |
DE60137324D1 (de) | 2009-02-26 |
JP2015073313A (ja) | 2015-04-16 |
WO2001069837A9 (en) | 2003-02-27 |
JP5237985B2 (ja) | 2013-07-17 |
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