JP5198760B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5198760B2 JP5198760B2 JP2006331619A JP2006331619A JP5198760B2 JP 5198760 B2 JP5198760 B2 JP 5198760B2 JP 2006331619 A JP2006331619 A JP 2006331619A JP 2006331619 A JP2006331619 A JP 2006331619A JP 5198760 B2 JP5198760 B2 JP 5198760B2
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- 239000004065 semiconductor Substances 0.000 title claims description 74
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 54
- 238000010438 heat treatment Methods 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 5
- 241000287463 Phalacrocorax Species 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 70
- 238000005229 chemical vapour deposition Methods 0.000 description 29
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 16
- 229910052698 phosphorus Inorganic materials 0.000 description 16
- 239000011574 phosphorus Substances 0.000 description 16
- 239000012535 impurity Substances 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
[第1の実施形態]
図1は、本発明の第1の実施形態に係る半導体装置10の縦断面図である。以下、「n+型」は、高濃度のn型不純物がドープされたn型半導体を示し、「n−型」は、低濃度のn型不純物がドープされたn型半導体を示す。同様に、「p+型」は、高濃度のp型不純物がドープされたp型半導体を示し、「p−型」は、低濃度のp型不純物がドープされたp型半導体を示している。また、図1の紙面左右方向を「X方向」と定義し、紙面上下方向を「Y方向」と定義する。
図5は、本発明の第2の実施形態に係る半導体装置40の構成を示す縦断面図である。第2の実施形態の特徴は、HTO酸化膜16の下にNSG(Non-doped Silicate Glass)膜41が形成されている点にある。以下、略同一構成については同一符号を付すこととする。
12...n−型エピタキシャル層
13...ゲートトレンチ
14...ゲート絶縁膜
15...ポリシリコン
16...HTO膜
17...p型ベース拡散層
18...n+型ソース拡散層
19...BPSG膜
20...CVD酸化膜
21...ソース電極
22...ドレイン電極
41...NSG膜
Claims (11)
- 半導体基板の表面及び半導体基板に形成されたトレンチ内のポリシリコンの上を覆うように前記トレンチ内に第3酸化膜を形成し、
前記第3酸化膜の上に第1酸化膜を形成し、
前記第1酸化膜を介して半導体基板に第1導電型のベース拡散層及び第2導電型のソース拡散層を形成し、
前記第1酸化膜の上に第2酸化膜を形成し、
前記第2酸化膜の上にリフロー性を有する絶縁膜を形成し、
前記絶縁膜を平坦化すると共に前記ソース拡散層を所定の深さまで拡散させる熱処理を行い、
平坦化された前記絶縁膜の表面から前記トレンチの間口部までエッチングを行う半導体装置の製造方法。 - 前記リフロー性を有する絶縁膜は、BPSG膜である請求項1記載の半導体装置の製造方法。
- 前記第2酸化膜の膜厚は、前記熱処理の温度が900℃以下であるときは24Åより厚い請求項1又は2記載の半導体装の製造方法。
- 前記第2酸化膜の膜厚は、前記熱処理の温度が950℃以下であるときは80Åより厚い請求項1又は2記載の半導体装置の製造方法。
- 前記第2酸化膜の膜厚は、前記熱処理の温度が1000℃以下であるときは200Åより厚い請求項1又は2記載の半導体装置の製造方法。
- 前記第2酸化膜の膜厚は、前記熱処理の温度が1100℃以下であるときは1200Åより厚い請求項1又は2記載の半導体装置の製造方法。
- 前記第2酸化膜は、CVD酸化膜である請求項1〜6のうちいずれか1項に記載の半導体装置の製造方法。
- 前記第3酸化膜は、NSG膜である請求項1〜7のうちいずれか1項に記載の半導体装置の製造方法。
- 半導体基板と、
この半導体基板上に形成された第2導電型の第1のドレイン領域と、
前記第1のドレイン領域上に形成された第1導電型のベース拡散領域と、
前記拡散領域の表面に選択的に形成された第2導電型のソース拡散領域と、
前記半導体基板の主面から、底面が前記ドレイン領域に位置するように形成されたトレンチと、
前記トレンチの側面に形成された絶縁膜と、
前記絶縁膜上に形成されたポリシリコンと、
前記トレンチ内に埋め込まれ、前記ポリシリコン上に形成された第1酸化膜と、
前記トレンチ内に埋め込まれ、前記第1酸化膜上に形成された第2酸化膜と、
前記トレンチ内に埋め込まれ、前記ポリシリコンと前記第1酸化膜との間に形成された第3酸化膜とを有する半導体装置。 - 前記第2酸化膜上に形成されたリフロー性を有する絶縁膜を更に有する請求項9記載の半導体装置。
- 前記第2酸化膜の膜厚は、24〜10000Åである請求項9又は10記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006331619A JP5198760B2 (ja) | 2006-12-08 | 2006-12-08 | 半導体装置及びその製造方法 |
US11/984,043 US7704827B2 (en) | 2006-12-08 | 2007-11-13 | Semiconductor device and method for manufacturing the same |
US12/659,454 US8072026B2 (en) | 2006-12-08 | 2010-03-09 | Semiconductor device and method for manufacturing the same |
US13/317,781 US8310005B2 (en) | 2006-12-08 | 2011-10-28 | Semiconductor device and method for manufacturing the same |
US13/669,056 US8592896B2 (en) | 2006-12-08 | 2012-11-05 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2006331619A JP5198760B2 (ja) | 2006-12-08 | 2006-12-08 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008147339A JP2008147339A (ja) | 2008-06-26 |
JP5198760B2 true JP5198760B2 (ja) | 2013-05-15 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006331619A Expired - Fee Related JP5198760B2 (ja) | 2006-12-08 | 2006-12-08 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
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US (4) | US7704827B2 (ja) |
JP (1) | JP5198760B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20100065895A (ko) * | 2008-12-09 | 2010-06-17 | 주식회사 동부하이텍 | 트렌치형 mosfet 소자의 게이트 및 게이트 형성방법 |
JP5626356B2 (ja) | 2010-05-27 | 2014-11-19 | 富士電機株式会社 | Mos駆動型半導体装置およびmos駆動型半導体装置の製造方法 |
JP5774921B2 (ja) * | 2011-06-28 | 2015-09-09 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体装置の製造方法、及び電子装置 |
US9130060B2 (en) | 2012-07-11 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having a vertical power MOS transistor |
US8669611B2 (en) * | 2012-07-11 | 2014-03-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for power MOS transistor |
CN104659112A (zh) * | 2015-03-09 | 2015-05-27 | 江苏中科君芯科技有限公司 | 降低动态损耗的沟槽式二极管结构 |
JP6080883B2 (ja) * | 2015-03-11 | 2017-02-15 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2018182032A (ja) * | 2017-04-11 | 2018-11-15 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
CN109524470A (zh) * | 2018-10-29 | 2019-03-26 | 上海华力集成电路制造有限公司 | Nmos管及其制造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6351009B1 (en) | 1999-03-01 | 2002-02-26 | Fairchild Semiconductor Corporation | MOS-gated device having a buried gate and process for forming same |
JP4186318B2 (ja) | 1999-07-19 | 2008-11-26 | 富士電機デバイステクノロジー株式会社 | 半導体装置の製造方法 |
GB9929613D0 (en) * | 1999-12-15 | 2000-02-09 | Koninkl Philips Electronics Nv | Manufacture of semiconductor material and devices using that material |
US6403432B1 (en) * | 2000-08-15 | 2002-06-11 | Taiwan Semiconductor Manufacturing Company | Hardmask for a salicide gate process with trench isolation |
US6465325B2 (en) * | 2001-02-27 | 2002-10-15 | Fairchild Semiconductor Corporation | Process for depositing and planarizing BPSG for dense trench MOSFET application |
JP2003101027A (ja) | 2001-09-27 | 2003-04-04 | Toshiba Corp | 半導体装置及びその製造方法 |
WO2003046999A1 (fr) * | 2001-11-30 | 2003-06-05 | Shindengen Electric Manufacturing Co., Ltd. | Dispositif a semi-conducteurs et procede de fabrication |
KR20050085617A (ko) * | 2002-12-14 | 2005-08-29 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 트렌치-게이트 실리콘 반도체 장치 및 그의 제조 방법 |
US6861701B2 (en) * | 2003-03-05 | 2005-03-01 | Advanced Analogic Technologies, Inc. | Trench power MOSFET with planarized gate bus |
JP2005086140A (ja) | 2003-09-11 | 2005-03-31 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP4860122B2 (ja) | 2004-06-25 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20080166854A1 (en) * | 2005-09-09 | 2008-07-10 | Dong-Suk Shin | Semiconductor devices including trench isolation structures and methods of forming the same |
TWI299519B (en) * | 2005-09-28 | 2008-08-01 | Promos Technologies Inc | Method of fabricating shallow trench isolation structure |
KR100816749B1 (ko) * | 2006-07-12 | 2008-03-27 | 삼성전자주식회사 | 소자분리막, 상기 소자분리막을 구비하는 비휘발성 메모리소자, 그리고 상기 소자분리막 및 비휘발성 메모리 소자형성 방법들 |
-
2006
- 2006-12-08 JP JP2006331619A patent/JP5198760B2/ja not_active Expired - Fee Related
-
2007
- 2007-11-13 US US11/984,043 patent/US7704827B2/en active Active
-
2010
- 2010-03-09 US US12/659,454 patent/US8072026B2/en active Active
-
2011
- 2011-10-28 US US13/317,781 patent/US8310005B2/en active Active
-
2012
- 2012-11-05 US US13/669,056 patent/US8592896B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8310005B2 (en) | 2012-11-13 |
US20120043604A1 (en) | 2012-02-23 |
US8592896B2 (en) | 2013-11-26 |
US8072026B2 (en) | 2011-12-06 |
US20100171172A1 (en) | 2010-07-08 |
US20130062689A1 (en) | 2013-03-14 |
US7704827B2 (en) | 2010-04-27 |
JP2008147339A (ja) | 2008-06-26 |
US20080135921A1 (en) | 2008-06-12 |
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