JP4829473B2 - 絶縁ゲート型半導体装置およびその製造方法 - Google Patents
絶縁ゲート型半導体装置およびその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims description 56
- 239000011229 interlayer Substances 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 45
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- 239000012535 impurity Substances 0.000 claims description 28
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
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- 230000002093 peripheral effect Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0869—Shape
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
することを特徴とするものである。
1a N+型シリコン半導体基板
1b N−型エピタキシャル層
3 チャネル層
5 トレンチ
6 ゲート酸化膜
7 ゲート電極
10 層間絶縁膜
11 凹部
12 ソース領域
13 ボディ領域
14 ソース電極
21 基板
21a N+型シリコン半導体基板
21b N−型エピタキシャル層
24 チャネル層
27 トレンチ
31 ゲート酸化膜
33 ゲート電極
34 ボディ領域
35 ソース領域
36 層間絶縁膜
37 ソース電極
50 空隙
Claims (10)
- ドレイン領域となる一導電型の半導体基板と、
前記ドレイン領域表面に設けた逆導電型のチャネル層と、
前記チャネル層を貫通して設けたトレンチと、
該トレンチの内壁に設けたゲート絶縁膜と、
前記トレンチに埋め込まれたゲート電極と、
隣り合う前記トレンチ間に設けられ、該トレンチに隣接する深い領域と、隣り合う該深い領域間の浅い領域とを有する一導電型のソース領域と、
隣り合う前記トレンチ間の前記基板表面に前記浅い領域を貫通して設けられた凹部と、
該凹部の底部に設けられた逆導電型のボディ領域と、
前記トレンチに埋め込まれ、周辺部より中心付近の膜厚が薄い層間絶縁膜と、
前記ゲート電極上をほぼ平坦に覆い、前記ソース領域とコンタクトするソース電極とを具備することを特徴とする絶縁ゲート型半導体装置。 - 前記ボディ領域は、前記チャネル層表面より下方で前記ソース電極とコンタクトすることを特徴とする請求項1に記載の絶縁ゲート型半導体装置。
- 前記凹部側壁に前記ソース領域が露出することを特徴とする請求項1に記載の絶縁ゲート型半導体装置。
- 一導電型の半導体基板表面に逆導電型のチャネル層を形成する工程と、
前記チャネル層を貫通するトレンチを形成する工程と、
前記トレンチの内壁にゲート絶縁膜を形成する工程と、
前記トレンチに埋め込まれその上部が該トレンチの開口部より下方に位置するゲート電極を形成する工程と、
前記ゲート電極上方で前記トレンチ内に埋め込まれ、周辺部より中心付近の膜厚が薄い層間絶縁膜を形成する工程と、
全面に一導電型不純物領域を形成する工程と、
隣り合う前記トレンチ間の前記一導電型不純物領域を分割する凹部を形成する工程と、
前記トレンチに隣接する深い領域と、隣り合う該深い領域間の浅い領域とを有する一導電型のソース領域を形成し、前記凹部の底部に逆導電型のボディ領域を形成する工程と、
前記ゲート電極上をほぼ平坦に覆うソース電極を形成する工程とを具備することを特徴とする絶縁ゲート型半導体装置の製造方法。 - 前記層間絶縁膜の上部表面は前記基板表面とほぼ同一平面上に形成されることを特徴とする請求項4に記載の絶縁ゲート型半導体装置の製造方法。
- 前記一導電型不純物領域を拡散して前記ソース領域を形成することを特徴とする請求項4に記載の絶縁ゲート型半導体装置の製造方法。
- 前記一導電型不純物領域を形成するイオンはトレンチ側面に対して斜めに注入されることを特徴とする請求項4に記載の絶縁ゲート型半導体装置の製造方法。
- 前記層間絶縁膜の形成工程から前記ソース領域および前記ボディ領域の形成工程までに用いるマスクは1枚であることを特徴とする請求項4に記載の絶縁ゲート型半導体装置の製造方法。
- 前記ゲート電極の形成後前記一導電型不純物領域を形成し、引き続き前記層間絶縁膜を形成した後前記マスクを設けて前記凹部を形成し、前記マスクを介して前記ボディ領域の不純物をイオン注入することを特徴とする請求項4に記載の絶縁ゲート型半導体装置の製造方法。
- 前記ソース領域と前記ボディ領域は一の熱処理工程にて同時に拡散形成されることを特徴とする請求項4に記載の絶縁ゲート型半導体装置の製造方法。
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JP2004013426A JP4829473B2 (ja) | 2004-01-21 | 2004-01-21 | 絶縁ゲート型半導体装置およびその製造方法 |
TW093131115A TWI254452B (en) | 2004-01-21 | 2004-10-14 | Insulation gate type semiconductor device and its manufacture method |
KR1020040111716A KR100576670B1 (ko) | 2004-01-21 | 2004-12-24 | 절연 게이트형 반도체 장치 및 그 제조 방법 |
CNB2004101037160A CN100449781C (zh) | 2004-01-21 | 2004-12-28 | 绝缘栅极型半导体装置及其制造方法 |
US11/023,961 US7629644B2 (en) | 2004-01-21 | 2004-12-29 | Insulated gate-type semiconductor device and manufacturing method of the same |
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JP2004013426A JP4829473B2 (ja) | 2004-01-21 | 2004-01-21 | 絶縁ゲート型半導体装置およびその製造方法 |
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JP2005209807A JP2005209807A (ja) | 2005-08-04 |
JP4829473B2 true JP4829473B2 (ja) | 2011-12-07 |
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JP2004013426A Expired - Fee Related JP4829473B2 (ja) | 2004-01-21 | 2004-01-21 | 絶縁ゲート型半導体装置およびその製造方法 |
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US (1) | US7629644B2 (ja) |
JP (1) | JP4829473B2 (ja) |
KR (1) | KR100576670B1 (ja) |
CN (1) | CN100449781C (ja) |
TW (1) | TWI254452B (ja) |
Families Citing this family (38)
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US8183629B2 (en) * | 2004-05-13 | 2012-05-22 | Vishay-Siliconix | Stacked trench metal-oxide-semiconductor field effect transistor device |
JP5110776B2 (ja) * | 2004-07-01 | 2012-12-26 | セイコーインスツル株式会社 | 半導体装置の製造方法 |
DE102004034472A1 (de) † | 2004-07-15 | 2006-02-09 | Spiess, Heike | Gedämpfter Lüfter |
JP4731848B2 (ja) * | 2004-07-16 | 2011-07-27 | 株式会社豊田中央研究所 | 半導体装置 |
JP4955222B2 (ja) * | 2005-05-20 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20060273384A1 (en) * | 2005-06-06 | 2006-12-07 | M-Mos Sdn. Bhd. | Structure for avalanche improvement of ultra high density trench MOSFET |
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US8471390B2 (en) * | 2006-05-12 | 2013-06-25 | Vishay-Siliconix | Power MOSFET contact metallization |
JP2008098593A (ja) * | 2006-09-15 | 2008-04-24 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
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JP6968042B2 (ja) * | 2018-07-17 | 2021-11-17 | 三菱電機株式会社 | SiC−SOIデバイスおよびその製造方法 |
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JP2003303967A (ja) * | 2002-04-09 | 2003-10-24 | Shindengen Electric Mfg Co Ltd | 半導体装置およびその製造方法 |
JP3640945B2 (ja) * | 2002-09-02 | 2005-04-20 | 株式会社東芝 | トレンチゲート型半導体装置及びその製造方法 |
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US7629644B2 (en) | 2009-12-08 |
KR20050076601A (ko) | 2005-07-26 |
US20050167748A1 (en) | 2005-08-04 |
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KR100576670B1 (ko) | 2006-05-08 |
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