JP6460016B2 - スイッチング素子 - Google Patents
スイッチング素子 Download PDFInfo
- Publication number
- JP6460016B2 JP6460016B2 JP2016046134A JP2016046134A JP6460016B2 JP 6460016 B2 JP6460016 B2 JP 6460016B2 JP 2016046134 A JP2016046134 A JP 2016046134A JP 2016046134 A JP2016046134 A JP 2016046134A JP 6460016 B2 JP6460016 B2 JP 6460016B2
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- Prior art keywords
- range
- metal layer
- region
- insulating film
- contact
- Prior art date
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- 239000010410 layer Substances 0.000 claims description 251
- 229910052751 metal Inorganic materials 0.000 claims description 222
- 239000002184 metal Substances 0.000 claims description 222
- 230000002093 peripheral effect Effects 0.000 claims description 130
- 239000004065 semiconductor Substances 0.000 claims description 88
- 210000000746 body region Anatomy 0.000 claims description 77
- 239000000758 substrate Substances 0.000 claims description 77
- 230000001681 protective effect Effects 0.000 claims description 64
- 239000011229 interlayer Substances 0.000 claims description 41
- 230000015556 catabolic process Effects 0.000 claims description 24
- 230000005684 electric field Effects 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 5
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
12 :第2素子範囲
13 :囲繞範囲
14 :外周耐圧範囲
18 :半導体基板
22 :エミッタ領域
24 :ボディ領域
26 :ドリフト領域
27 :バッファ領域
28 :コレクタ領域
29 :周辺p型領域
30 :ゲート電極
32 :ゲート絶縁膜
34 :終端領域
36 :ガードリング
40 :トレンチ
51 :オーミック金属層
52 :表面金属層
54 :下部電極
55 :はんだ層
60 :絶縁保護膜
62 :層間絶縁膜
Claims (2)
- 半導体基板とゲート絶縁膜とゲート電極と層間絶縁膜と第1金属層と第2金属層と絶縁保護膜を備えているスイッチング素子であり、
前記半導体基板が、第1素子範囲と、無効範囲を有しており、
前記第1素子範囲内の前記半導体基板の上面に、第1方向に沿って伸びる複数の第1トレンチが、前記第1方向に直交する第2方向に間隔を開けて設けられており、
前記無効範囲が、前記第2方向において前記第1素子範囲に隣接しており、
前記無効範囲内の前記上面に、前記第1トレンチが設けられておらず、
前記ゲート絶縁膜が、前記第1トレンチの内面を覆っており、
前記ゲート電極が、前記第1トレンチの内部に配置されており、前記ゲート絶縁膜によって前記半導体基板から絶縁されており、
前記層間絶縁膜が、前記上面と前記ゲート電極を覆っており、
前記第1素子範囲内では、前記上面を覆っている部分の前記層間絶縁膜にコンタクトホールが設けられており、
前記無効範囲内では、前記上面を覆っている部分の前記層間絶縁膜に、前記第2方向における幅が前記複数の第1トレンチの前記第2方向におけるピッチよりも広い幅広コンタクトホールが設けられており、
前記第1金属層が、前記層間絶縁膜を覆っており、前記層間絶縁膜によって前記ゲート電極から絶縁されており、前記コンタクトホール及び前記幅広コンタクトホール内で前記半導体基板に接しており、
前記第1金属層の表面には、前記コンタクトホールの上部に第1凹部が設けられているとともに前記幅広コンタクトホールの上部に第2凹部が設けられており、
前記絶縁保護膜が、前記第2凹部の底面の外周側の部分を覆っており、
前記絶縁保護膜には、前記第1素子範囲を含む前記第1素子範囲よりも広い範囲に開口が設けられており、前記開口の側面が前記第2凹部内に配置されており、
前記第2金属層が、前記開口内において前記第1金属層の前記表面に接しているとともに前記開口の前記側面に接しており、前記第1金属層よりも小さい線膨張係数を有しており、
前記第1素子範囲内の前記第1トレンチによって挟まれている各半導体領域が、
前記コンタクトホール内の前記第1金属層に接しており、前記ゲート絶縁膜に接している第1導電型の第1領域と、
前記コンタクトホール内の前記第1金属層に接しており、前記第1領域の下側で前記ゲート絶縁膜に接している第2導電型のボディ領域、
を備えており、
前記無効範囲内の半導体領域が、前記幅広コンタクトホール内の前記第1金属層に接しており、前記上面から前記第1トレンチの下端よりも深い位置まで伸びている第2導電型の周辺第2導電型領域を備えており、
前記半導体基板が、前記ボディ領域の下部と前記周辺第2導電型領域の下部に跨って配置されており、前記ボディ領域の下側で前記ゲート絶縁膜に接しており、かつ、前記ボディ領域によって前記第1領域から分離されている第1導電型の第2領域を備えており、
前記上面に、前記無効範囲の最も近くに位置する前記第1トレンチから前記無効範囲に向かって伸びる複数の第2トレンチが設けられており、
前記各第2トレンチの前記無効範囲側の端面が、前記周辺第2導電型領域に覆われている、
スイッチング素子。 - 半導体基板とゲート絶縁膜とゲート電極と層間絶縁膜と第1金属層と第2金属層と絶縁保護膜を備えているスイッチング素子であり、
前記半導体基板が、第1素子範囲と、無効範囲を有しており、
前記第1素子範囲内の前記半導体基板の上面に、第1方向に沿って伸びる複数の第1トレンチが、前記第1方向に直交する第2方向に間隔を開けて設けられており、
前記無効範囲が、前記第2方向において前記第1素子範囲に隣接しており、
前記無効範囲内の前記上面に、前記第1トレンチが設けられておらず、
前記ゲート絶縁膜が、前記第1トレンチの内面を覆っており、
前記ゲート電極が、前記第1トレンチの内部に配置されており、前記ゲート絶縁膜によって前記半導体基板から絶縁されており、
前記層間絶縁膜が、前記上面と前記ゲート電極を覆っており、
前記第1素子範囲内では、前記上面を覆っている部分の前記層間絶縁膜にコンタクトホールが設けられており、
前記無効範囲内では、前記上面を覆っている部分の前記層間絶縁膜に、前記第2方向における幅が前記複数の第1トレンチの前記第2方向におけるピッチよりも広い幅広コンタクトホールが設けられており、
前記第1金属層が、前記層間絶縁膜を覆っており、前記層間絶縁膜によって前記ゲート電極から絶縁されており、前記コンタクトホール及び前記幅広コンタクトホール内で前記半導体基板に接しており、
前記第1金属層の表面には、前記コンタクトホールの上部に第1凹部が設けられているとともに前記幅広コンタクトホールの上部に第2凹部が設けられており、
前記絶縁保護膜が、前記第2凹部の底面の外周側の部分を覆っており、
前記絶縁保護膜には、前記第1素子範囲を含む前記第1素子範囲よりも広い範囲に開口が設けられており、前記開口の側面が前記第2凹部内に配置されており、
前記第2金属層が、前記開口内において前記第1金属層の前記表面に接しているとともに前記開口の前記側面に接しており、前記第1金属層よりも小さい線膨張係数を有しており、
前記第1素子範囲内の前記第1トレンチによって挟まれている各半導体領域が、
前記コンタクトホール内の前記第1金属層に接しており、前記ゲート絶縁膜に接している第1導電型の第1領域と、
前記コンタクトホール内の前記第1金属層に接しており、前記第1領域の下側で前記ゲート絶縁膜に接している第2導電型のボディ領域、
を備えており、
前記無効範囲内の半導体領域が、前記幅広コンタクトホール内の前記第1金属層に接しており、前記上面から前記第1トレンチの下端よりも深い位置まで伸びている第2導電型の周辺第2導電型領域を備えており、
前記半導体基板が、前記ボディ領域の下部と前記周辺第2導電型領域の下部に跨って配置されており、前記ボディ領域の下側で前記ゲート絶縁膜に接しており、かつ、前記ボディ領域によって前記第1領域から分離されている第1導電型の第2領域を備えており、
前記半導体基板が、前記第1素子範囲と前記無効範囲を含む範囲の周囲を囲む外周耐圧範囲を有しており、
前記外周耐圧範囲内に、前記上面に露出しており、前記第1素子範囲と前記無効範囲を含む前記範囲を囲んでおり、前記第1金属層から電気的に分離されている第2導電型のガードリングが設けられており、
前記半導体基板が、前記無効範囲と前記外周耐圧範囲の間に配置されている第2素子範囲を有しており、
前記第2素子範囲内の前記上面に、複数の前記第1トレンチが、前記第2方向に間隔を開けて設けられており、
前記第2素子範囲内では、前記上面を覆っている部分の前記層間絶縁膜にコンタクトホールが設けられており、
前記第1金属層が、前記第2素子範囲内の前記コンタクトホール内で前記上面に接しており、
前記絶縁保護膜が、前記第2素子範囲内の前記第1金属層を覆っており、
前記第2金属層が、前記開口内の前記第1金属層上から前記絶縁保護膜上に跨って配置されており、
前記第2金属層の外周側端部が、前記第1金属層の外周側端部よりも内周側に位置しており、
前記第2素子範囲内の前記第1トレンチによって挟まれている各半導体領域が、前記第1領域と前記ボディ領域を有している、
スイッチング素子。
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