JP4627323B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4627323B2
JP4627323B2 JP2008004744A JP2008004744A JP4627323B2 JP 4627323 B2 JP4627323 B2 JP 4627323B2 JP 2008004744 A JP2008004744 A JP 2008004744A JP 2008004744 A JP2008004744 A JP 2008004744A JP 4627323 B2 JP4627323 B2 JP 4627323B2
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bga substrate
semiconductor device
semiconductor chip
substrate
semiconductor
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JP2008135772A (en
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伸治 馬場
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

本発明は、半導体装置に関し、特に有機材料を用いた基板を有する半導体装置に関する。   The present invention relates to a semiconductor device, and particularly to a semiconductor device having a substrate using an organic material.

図８は、従来の半導体層の断面図を示す。図８において、符号１７はセラミック材料を用いたセラミック基板、２はセラミック基板１７上にバンプ３を介してフリップチップ接合された半導体チップ、４は半導体チップ２とセラミック基板１７との間を充填するアンダーフィル樹脂、１２はスイッチングノイズを低減させるためにセラミック基板１７上に形成されたチップコンデンサ、９はセラミック基板１７の下面に形成された半田ボールである。   FIG. 8 shows a cross-sectional view of a conventional semiconductor layer. In FIG. 8, reference numeral 17 denotes a ceramic substrate using a ceramic material, 2 denotes a semiconductor chip flip-chip bonded to the ceramic substrate 17 via bumps 3, and 4 denotes a space between the semiconductor chip 2 and the ceramic substrate 17. An underfill resin, 12 is a chip capacitor formed on the ceramic substrate 17 to reduce switching noise, and 9 is a solder ball formed on the lower surface of the ceramic substrate 17.

図８に示されるように、従来の半導体装置は、特に電気的に高性能を要求される用途に対して、例えばセラミック材料を採用したＢＧＡ（Ball Grid Array）基板（セラミック基板１７）と半導体チップ２とをバンプ３を介してフリップチップ接合することにより、電気的接合距離を短くしていた。しかし、セラミック材料からなる半導体装置は、有機材料からなる実装基板と熱膨張係数が異なるため、実装信頼性を保つためには外形サイズの小さい領域、すなわち端子数の少ない領域でのみしかＢＧＡパッケージとして採用することができないという問題があった。したがって、外形サイズの大きい領域、すなわち端子数の多い領域ではＰＧＡ（Pin Grid Array）パッケージを採用することになるため、半導体装置を接続するソケットを半導体装置と実装基板との間に設ける必要があり、コストが余計にかかるという問題があった。   As shown in FIG. 8, the conventional semiconductor device has a BGA (Ball Grid Array) substrate (ceramic substrate 17) and a semiconductor chip that employ, for example, a ceramic material, especially for applications that require high electrical performance. 2 is flip-chip bonded via bumps 3 to shorten the electrical bonding distance. However, a semiconductor device made of a ceramic material has a thermal expansion coefficient different from that of a mounting board made of an organic material. Therefore, in order to maintain mounting reliability, a BGA package can be used only in a region having a small external size, that is, a region having a small number of terminals. There was a problem that it could not be adopted. Therefore, since a PGA (Pin Grid Array) package is adopted in a region having a large external size, that is, a region having a large number of terminals, it is necessary to provide a socket for connecting the semiconductor device between the semiconductor device and the mounting substrate. There was a problem that the cost was excessive.

図９は、図８のチップコンデンサ１２の電気的モデル図を示す。図９で図８と同じ符号を付した部分は同じ機能を有するため説明は省略する。図９において、符号１３ａは多層基板化された複数のセラミック基板１７中にある電源プレーン、１３ｂはセラミック基板１７中にあるグランドプレーン、１８は配線のインダクタンスである。   FIG. 9 shows an electrical model diagram of the chip capacitor 12 of FIG. 9 with the same reference numerals as those in FIG. 8 have the same functions, and thus description thereof is omitted. In FIG. 9, reference numeral 13a is a power plane in a plurality of ceramic substrates 17 formed into a multilayer substrate, 13b is a ground plane in the ceramic substrate 17, and 18 is an inductance of wiring.

従来、電子機器等の信号処理速度の高速化に伴いスイッチングノイズの問題が生じていたが、図９に示されるように、従来の半導体装置は、１０層以上の多層基板を採用し、電源プレーン１３ａとグランドプレーン１３ｂ（以下、まとめて呼ぶ場合は「電源／グランドプレーン１３」という）を増強することにより、スイッチングノイズを低減させて高性能を実現していた。この電源／グランドプレーン１３特性をさらに向上させるため、スイッチングノイズを吸収するためのノイズ吸収用コンデンサとして、セラミック基板１７上に高い容量を有するチップコンデンサ１２を配置していた。   Conventionally, there has been a problem of switching noise with an increase in signal processing speed of an electronic device or the like. However, as shown in FIG. 9, a conventional semiconductor device employs a multilayer substrate of 10 layers or more and a power plane. 13a and the ground plane 13b (hereinafter, collectively referred to as “power supply / ground plane 13”) enhance switching performance by reducing switching noise. In order to further improve the characteristics of the power / ground plane 13, a chip capacitor 12 having a high capacity is disposed on the ceramic substrate 17 as a noise absorbing capacitor for absorbing switching noise.

しかし、半導体チップ２の横にチップコンデンサ１２を設けた場合、半導体チップ２とチップコンデンサ１２とを接続する配線距離が長くなり、配線のインダクタンス１８が大きくなるため、スイッチングノイズを低減させるという電気的な高性能を満足させるために低インダクタンスのチップコンデンサ１２を採用したとしても、十分にその性能を発揮することができないという問題があった。さらにチップコンデンサ１２自体のコストが高いという問題もあった。   However, when the chip capacitor 12 is provided beside the semiconductor chip 2, the wiring distance for connecting the semiconductor chip 2 and the chip capacitor 12 becomes long and the wiring inductance 18 becomes large. Even if the low-inductance chip capacitor 12 is used to satisfy the high performance, there is a problem that the performance cannot be sufficiently exhibited. Further, there is a problem that the cost of the chip capacitor 12 itself is high.

そこで、本発明の目的は、上記問題を解決するためになされたものであり、端子数が多い場合であっても実装信頼性を高くしつつ、かつ安価に実現可能な多ピンの半導体記憶装置を提供することにある。さらに、本発明の目的は、端子数が多い場合であっても、電源／グランドプレーン特性を高くしつつ、かつ安価に実現可能な多ピンの半導体記憶装置を提供することにある。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problem, and is a multi-pin semiconductor memory device that can be realized at low cost while increasing mounting reliability even when the number of terminals is large. Is to provide. It is another object of the present invention to provide a multi-pin semiconductor memory device that can be realized at low cost while improving the power / ground plane characteristics even when the number of terminals is large.

この発明の半導体装置は、有機材料を用いて形成された、多層構造のＢＧＡ基板、複数のバンプを介して該ＢＧＡ基板の主面に接合された半導体チップを備える。また、該主面と対向する該ＢＧＡ基板の反対側の面であって、該半導体チップのエッジ部分に対応する位置に形成され、電源とグランドとを接続するチップコンデンサを備える。   A semiconductor device according to the present invention includes a BGA substrate having a multilayer structure formed using an organic material, and a semiconductor chip bonded to the main surface of the BGA substrate through a plurality of bumps. In addition, a chip capacitor is provided on the opposite surface of the BGA substrate that faces the main surface and corresponding to the edge portion of the semiconductor chip, and connects the power source and the ground.

本発明によれば、端子数が多い場合であっても実装信頼性を高くしつつ、かつ安価に実現可能な多ピンの半導体記憶装置を提供することができる。さらに、本発明の半導体記憶装置によれば、端子数が多い場合であっても、電源／グランドプレーン特性を高くしつつ、かつ安価に実現可能な多ピンの半導体記憶装置を提供することができる。   According to the present invention, it is possible to provide a multi-pin semiconductor memory device that can be implemented at low cost while increasing mounting reliability even when the number of terminals is large. Furthermore, according to the semiconductor memory device of the present invention, even when the number of terminals is large, it is possible to provide a multi-pin semiconductor memory device that can be realized at low cost while improving the power / ground plane characteristics. .

以下、図面を参照して、本発明の実施の形態を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

実施の形態１
図１は、本発明の実施の形態１における半導体装置の断面図を示す。図１において、符号１は有機材料を用いたＢＧＡ基板、２はＢＧＡ基板１上にバンプ３を介してフリップチップ接合された半導体チップ、４は半導体チップ２とＢＧＡ基板１との間を充填するアンダーフィル樹脂、７はＢＧＡ基板１の上面にリング接着剤５を介して取り付けられたリング、８は半導体チップ２とリング７との上面に、半導体チップ１側はヒートスプレッダ接着剤を介しリング７側はリング接着剤５と同じ接着剤を介して取り付けられたヒートスプレッダ、９はＢＧＡ基板１の下面（または裏面）に形成された半田ボール、１０はスタックドヴィア（Stacked Via）である。 Embodiment 1
FIG. 1 shows a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 is a BGA substrate using an organic material, 2 is a semiconductor chip flip-bonded to the BGA substrate 1 via bumps 3, and 4 is a space between the semiconductor chip 2 and the BGA substrate 1. Underfill resin, 7 is a ring attached to the upper surface of the BGA substrate 1 via a ring adhesive 5, 8 is an upper surface of the semiconductor chip 2 and the ring 7, and the semiconductor chip 1 side is on the ring 7 side via a heat spreader adhesive Is a heat spreader attached via the same adhesive as the ring adhesive 5, 9 is a solder ball formed on the lower surface (or back surface) of the BGA substrate 1, and 10 is a stacked via.

ＢＧＡ基板１は、一般的に用いられている有機材料、例えばＦＲ４、ＢＴレシン等のエポキシ樹脂からなる実装基板１６（後述）と同等の熱膨張係数を有する有機材料からなっている。したがって、実装基板１６のサイズが大きくても半田ボール９の実装信頼性を高めることができるため、５００から１０００ピンクラスを越える多ピン端子数のＢＧＡタイプの半導体装置を実現することができる。この結果，従来の技術で説明されたようなＰＧＡタイプの半導体装置を用いた場合に必要であった実装用のソケット等を不用とすることができるため、コストの低減をすることが可能となる。   The BGA substrate 1 is made of a generally used organic material, for example, an organic material having a thermal expansion coefficient equivalent to that of a mounting substrate 16 (described later) made of an epoxy resin such as FR4 or BT resin. Accordingly, since the mounting reliability of the solder balls 9 can be increased even if the size of the mounting substrate 16 is large, a BGA type semiconductor device having a multi-pin terminal number exceeding 500 to 1000 pin classes can be realized. As a result, it is possible to eliminate a mounting socket or the like that is necessary when using a PGA type semiconductor device as described in the prior art, and thus it is possible to reduce costs. .

ＢＧＡ基板１は多層の構造を有しており、図１では８層の場合が例示されている。以下、本明細書において、特に多層の構造全体を指すためにＢＧＡ基板１に代えてパッケージ部１という語を用いる場合がある。図１に示されるように、多層に積層されたＢＧＡ基板１中にある各接続孔は、ＢＧＡ基板１が積層された方向（垂直方向）に垂直につなぎ合わされて、スタックドヴィアまたはスタックドバイア１０を形成している。このスタックドヴィア１０の水平方向のピッチは、半導体チップ１上に形成されたバンプ３の水平方向のピッチと同等のピッチを有している。   The BGA substrate 1 has a multi-layer structure, and FIG. 1 illustrates the case of eight layers. Hereinafter, in the present specification, the term “package part 1” may be used in place of the BGA substrate 1 in order to particularly indicate the entire multilayer structure. As shown in FIG. 1, each connection hole in a multilayered BGA substrate 1 is connected vertically to the direction (vertical direction) in which the BGA substrate 1 is stacked, so that stacked vias or stacked vias are formed. 10 is formed. The horizontal pitch of the stacked vias 10 is equal to the horizontal pitch of the bumps 3 formed on the semiconductor chip 1.

上述のようにスタックドヴィア１０を形成することにより、５００から１０００ピンクラスを越える多ピン端子数となった場合でも、信号用端子を自由度を高くフルマトリックス状に配置することができるため、半導体チップ２のサイズを小さくすることができ、半導体チップ２とＢＧＡ基板１との間のバンプ３の信頼性も高く、安価に多ピンの半導体を実現することができる。   By forming the stacked via 10 as described above, the signal terminals can be arranged in a full matrix with a high degree of freedom even when the number of multi-pin terminals exceeds 500 to 1000 pin classes. The size of the semiconductor chip 2 can be reduced, the reliability of the bump 3 between the semiconductor chip 2 and the BGA substrate 1 is high, and a multi-pin semiconductor can be realized at low cost.

以上より、実施の形態１によれば、実装基板１６のサイズが大きくても半田ボール９の実装信頼性を高めることができるため、５００から１０００ピンクラスを越える多ピン端子数のＢＧＡタイプの半導体装置を実現することができる。この結果，ＰＧＡタイプの半導体装置を用いた場合に必要であった実装用のソケット等を不用とすることができるため、コストの低減をすることが可能となる。さらに、多ピン端子数となった場合でも、信号用端子を自由度を高くフルマトリックス状に配置することができるため、半導体チップ２のサイズを小さくすることができ、半導体チップ２とＢＧＡ基板１との間のバンプ３の信頼性も高く、安価に多ピンの半導体装置を実現することができる。   As described above, according to the first embodiment, since the mounting reliability of the solder balls 9 can be improved even if the size of the mounting substrate 16 is large, a BGA type semiconductor having a multi-pin terminal number exceeding 500 to 1000 pin classes. An apparatus can be realized. As a result, a mounting socket or the like that is necessary when a PGA type semiconductor device is used can be made unnecessary, so that the cost can be reduced. Further, even when the number of pins is large, the signal terminals can be arranged in a full matrix with a high degree of freedom, so that the size of the semiconductor chip 2 can be reduced, and the semiconductor chip 2 and the BGA substrate 1 can be reduced. The reliability of the bump 3 between the two is high, and a multi-pin semiconductor device can be realized at low cost.

実施の形態２
図２は、本発明の実施の形態２における半導体装置の断面図を示す。図２で図１と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図２において、符号１１は高誘電率の材料からなる高誘電率層（キャパシタ層）である。 Embodiment 2
FIG. 2 is a sectional view of the semiconductor device according to the second embodiment of the present invention. 2 that have the same reference numerals as those in FIG. 1 have the same functions, and therefore description thereof is omitted. In FIG. 2, reference numeral 11 denotes a high dielectric constant layer (capacitor layer) made of a high dielectric constant material.

図２に示されるように、本発明の実施の形態２においては実施の形態１の構造を有するパッケージ部１に加えて、有機材料を用いたＢＧＡ基板１の内部にある電源プレーン１３ａとグランドプレーン１３ｂとの間にのみ高誘電率層１１を設けている。   As shown in FIG. 2, in the second embodiment of the present invention, in addition to the package portion 1 having the structure of the first embodiment, a power plane 13a and a ground plane inside the BGA substrate 1 using an organic material are used. The high dielectric constant layer 11 is provided only between 13b.

図３は、図２の高誘電率層の機能を説明するための半導体装置の断面図を示す。図３で図１または図２と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図３に示されるように、電源／グランドプレーン１３間に形成された高誘電率層１１によるキャパシタ１１aにより、バンプ３と電源／グランドプレーンとの間のインダクタンス１９を極限まで低減させることができ、有効にスイッチングノイズを低減させることができる。   FIG. 3 is a cross-sectional view of the semiconductor device for explaining the function of the high dielectric constant layer of FIG. 3 that have the same reference numerals as those in FIG. 1 or FIG. 2 have the same functions, and therefore description thereof is omitted. As shown in FIG. 3, the capacitor 11a formed by the high dielectric constant layer 11 formed between the power supply / ground plane 13 can reduce the inductance 19 between the bump 3 and the power supply / ground plane to the limit, Switching noise can be effectively reduced.

以上より、実施の形態２によれば、実施の形態１の構造を有するパッケージ部１に加えて、有機材料を用いたＢＧＡ基板１の内部にある電源プレーン１３ａとグランドプレーン１３ｂとの間にのみ高誘電率層１１を設けることにより、バンプ３と電源／グランドプレーンとの間のインダクタンス１９を極限まで低減させることができ、有効にスイッチングノイズを低減させることができる。   As described above, according to the second embodiment, in addition to the package unit 1 having the structure of the first embodiment, only between the power plane 13a and the ground plane 13b inside the BGA substrate 1 using an organic material. By providing the high dielectric constant layer 11, the inductance 19 between the bump 3 and the power supply / ground plane can be reduced to the limit, and the switching noise can be effectively reduced.

実施の形態３
図４は、本発明の実施の形態３における半導体装置の断面図を示す。図４で図１ないし図３と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図４において、符号１２はＢＧＡ基板１の下面に取り付けられたチップコンデンサである。 Embodiment 3
FIG. 4 is a sectional view of the semiconductor device according to the third embodiment of the present invention. In FIG. 4, the portions denoted by the same reference numerals as those in FIGS. 1 to 3 have the same functions, and thus the description thereof is omitted. In FIG. 4, reference numeral 12 denotes a chip capacitor attached to the lower surface of the BGA substrate 1.

図４に示されるように、本発明の実施の形態３においては実施の形態１の構造を有するパッケージ部１において、実装信頼性が一般的には最も低いとされている半導体チップ２のエッジ下方の半田ボール９の位置にチップコンデンサ１２を取り付けることにより、電源／グランドプレーン１３の電気的特性を高めることができる。５００または７００から１０００ピンクラスを越える多ピン端子数の要求に対しても、上述のように信号用端子として用いられない半導体チップ２のエッジ下方のみに限定してチップコンデンサ１２を取り付けるため、実質的に実装信頼性上、多ピンの要求を一切妨げることがない。さらに、従来の半導体チップ１２の横にチップコンデンサ１２を設ける場合と比較して、バンプ３からの距離を短くすることができるため、配線によるインダクタンス１９を低減させることができ、同等の性能を有するチップコンデンサ１２を用いたとしても、さらに有効にスイッチングノイズを低減させることができる。   As shown in FIG. 4, in the third embodiment of the present invention, in the package portion 1 having the structure of the first embodiment, the lower part of the edge of the semiconductor chip 2 that is generally considered to have the lowest mounting reliability. The electrical characteristics of the power / ground plane 13 can be enhanced by attaching the chip capacitor 12 to the position of the solder ball 9. Since the chip capacitor 12 is attached only to the lower part of the edge of the semiconductor chip 2 that is not used as a signal terminal as described above, the chip capacitor 12 is substantially attached to the demand for the number of multi-pin terminals exceeding 500 or 700 to 1000 pin classes. In terms of mounting reliability, it does not hinder the requirement for multiple pins. Furthermore, since the distance from the bump 3 can be shortened as compared with the case where the chip capacitor 12 is provided beside the conventional semiconductor chip 12, the inductance 19 due to the wiring can be reduced and the performance is equivalent. Even if the chip capacitor 12 is used, switching noise can be reduced more effectively.

以上より、実施の形態３によれば、実施の形態１の構造を有するパッケージ部１において、実装信頼性が一般的には最も低いとされている半導体チップ２のエッジ下方の半田ボール９の位置にチップコンデンサ１２を取り付けることにより、電源／グランドプレーン１３の電気的特性を高めることができる。   As described above, according to the third embodiment, in the package unit 1 having the structure of the first embodiment, the position of the solder ball 9 below the edge of the semiconductor chip 2 that is generally considered to have the lowest mounting reliability. The electrical characteristics of the power / ground plane 13 can be enhanced by attaching the chip capacitor 12 to the power supply / ground plane 13.

実施の形態４
図５は、本発明の実施の形態４における半導体装置の断面図を示す。図５で図１ないし図４と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図５において、符号１４はＢＧＡ基板１とリング７との間に用いられる高誘電材接着剤である。 Embodiment 4
FIG. 5 shows a sectional view of the semiconductor device according to the fourth embodiment of the present invention. In FIG. 5, the portions denoted by the same reference numerals as those in FIGS. 1 to 4 have the same functions, and thus description thereof is omitted. In FIG. 5, reference numeral 14 denotes a high dielectric material adhesive used between the BGA substrate 1 and the ring 7.

図５に示されるように、本発明の実施の形態４においては実施の形態１のＢＧＡ基板１とリング７との接着剤として、高誘電材の接着剤１４を用いることにより、チップコンデンサ１２を取り付けることなく、電源／グランドプレーン１３間の電気的特性を高めることができ、有効にスイッチングノイズを低減させることができる。   As shown in FIG. 5, in the fourth embodiment of the present invention, a chip capacitor 12 is formed by using a high dielectric material adhesive 14 as an adhesive between the BGA substrate 1 and the ring 7 of the first embodiment. Without mounting, the electrical characteristics between the power supply / ground plane 13 can be enhanced, and the switching noise can be effectively reduced.

以上より、実施の形態４によれば、実施の形態１の構造を有するパッケージ部上面のＢＧＡ基板１とリング７との接着剤として、高誘電材の接着剤１４を用いることにより、チップコンデンサ１２を取り付けることなく、電源／グランドプレーン１３間の電気的特性を高めることができ、有効にスイッチングノイズを低減させることができる。   As described above, according to the fourth embodiment, the chip capacitor 12 is obtained by using the high dielectric material adhesive 14 as the adhesive between the BGA substrate 1 and the ring 7 on the upper surface of the package portion having the structure of the first embodiment. Therefore, the electrical characteristics between the power supply / ground plane 13 can be improved and the switching noise can be effectively reduced.

実施の形態５
図６は、本発明の実施の形態５における半導体装置の断面図を示す。図６で図１ないし図５と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図６において、符号１５はＢＧＡ基板１とリング７との間に用いられる高誘電材接着剤である。 Embodiment 5
FIG. 6 is a sectional view of the semiconductor device according to the fifth embodiment of the present invention. In FIG. 6, the same reference numerals as those in FIGS. 1 to 5 have the same functions, and thus description thereof is omitted. In FIG. 6, reference numeral 15 denotes a high dielectric material adhesive used between the BGA substrate 1 and the ring 7.

図６に示されるように、本発明の実施の形態５においては実施の形態１のパッケージ部１の下面（裏面）であって、かつ半導体チップ２の搭載位置の下方に、高誘電率の材料からなる接着シート（高誘電材テープ）１５を貼り付けることにより、電源／グランドプレーン１３間の電気的特性を高めることができ、有効にスイッチングノイズを低減させることができる。   As shown in FIG. 6, in the fifth embodiment of the present invention, a high dielectric constant material is provided on the lower surface (back surface) of the package portion 1 of the first embodiment and below the mounting position of the semiconductor chip 2. By adhering the adhesive sheet (high dielectric material tape) 15 made of the above, the electrical characteristics between the power supply / ground plane 13 can be enhanced, and the switching noise can be effectively reduced.

以上より、実施の形態５によれば、実施の形態１の構造を有するパッケージ部１の下面（裏面）であって、かつ半導体チップ２の搭載位置の下方に、高誘電率の材料からなる接着シート（高誘電材テープ）１５を貼り付けることにより、電源／グランドプレーン１３間の電気的特性を高めることができ、有効にスイッチングノイズを低減させることができる。   As described above, according to the fifth embodiment, an adhesive made of a material having a high dielectric constant is provided on the lower surface (back surface) of the package unit 1 having the structure of the first embodiment and below the mounting position of the semiconductor chip 2. By attaching the sheet (high dielectric tape) 15, the electrical characteristics between the power supply / ground plane 13 can be enhanced, and the switching noise can be effectively reduced.

実施の形態６
図７は、本発明の実施の形態６における半導体装置の断面図を示す。図７で図１ないし図６と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図７において、符号１６はパッケージ部１を実装する実装基板である。 Embodiment 6
FIG. 7 is a sectional view of the semiconductor device according to the sixth embodiment of the present invention. In FIG. 7, the portions denoted by the same reference numerals as those in FIGS. 1 to 6 have the same functions, and thus description thereof is omitted. In FIG. 7, reference numeral 16 denotes a mounting substrate on which the package unit 1 is mounted.

図７に示されるように、本発明の実施の形態６においては実施の形態１のパッケージ部１を実装する実装基板１６上であって、かつ半導体チップ２の搭載位置の下方に、高誘電率の材料からなる接着シート（高誘電材テープ）１５を貼り付けることにより、電源／グランドプレーン１３間の電気的特性を高めることができ、有効にスイッチングノイズを低減させることができる。   As shown in FIG. 7, in the sixth embodiment of the present invention, a high dielectric constant is provided on the mounting substrate 16 on which the package unit 1 of the first embodiment is mounted and below the mounting position of the semiconductor chip 2. By adhering the adhesive sheet (high dielectric tape) 15 made of the above material, the electrical characteristics between the power source / ground plane 13 can be enhanced, and the switching noise can be effectively reduced.

以上より、実施の形態６によれば、実施の形態１のパッケージ部１を実装する実装基板１６上であって、かつ半導体チップ２の搭載位置の下方に、高誘電率の材料からなる接着シート（高誘電材テープ）１５を貼り付けることにより、電源／グランドプレーン１３間の電気的特性を高めることができ、有効にスイッチングノイズを低減させることができる。   As described above, according to the sixth embodiment, the adhesive sheet made of a high dielectric constant material is mounted on the mounting substrate 16 on which the package unit 1 of the first embodiment is mounted and below the mounting position of the semiconductor chip 2. By affixing (high dielectric tape) 15, the electrical characteristics between the power supply / ground plane 13 can be enhanced, and switching noise can be effectively reduced.

本発明の実施の形態１における半導体装置の断面図である。It is sectional drawing of the semiconductor device in Embodiment 1 of this invention. 本発明の実施の形態２における半導体装置の断面図である。It is sectional drawing of the semiconductor device in Embodiment 2 of this invention. 図２の高誘電率層の機能を説明するための半導体装置の断面図である。It is sectional drawing of the semiconductor device for demonstrating the function of the high dielectric constant layer of FIG. 本発明の実施の形態３における半導体装置の断面図である。It is sectional drawing of the semiconductor device in Embodiment 3 of this invention. 本発明の実施の形態４における半導体装置の断面図である。It is sectional drawing of the semiconductor device in Embodiment 4 of this invention. 本発明の実施の形態５における半導体装置の断面図である。It is sectional drawing of the semiconductor device in Embodiment 5 of this invention. 本発明の実施の形態６における半導体装置の断面図である。It is sectional drawing of the semiconductor device in Embodiment 6 of this invention. 従来の半導体層の断面図である。It is sectional drawing of the conventional semiconductor layer. 図８のチップコンデンサ１２の配置を示す図である。It is a figure which shows arrangement | positioning of the chip capacitor 12 of FIG.

符号の説明Explanation of symbols

１ ＢＧＡ基板、 ２ 半導体チップ、 ３ バンプ、 ４ アンダーフィル樹脂、 ５ リング接着剤、 ６ ヒートスプレッダ接着剤、 ７ リング、８ ヒートスプレッダ、 ９ 半導体ボール、 １０ スタックドヴィア、 １１ 高誘電率層、 １１ａ 高誘電率層１１によるキャパシタ、 １２ チップコンデンサ、 １３ 電源／グランドプレーン、 １３ａ 電源プレーン、 １３ｂ グランドプレーン、 １４ 高誘電材接着剤、 １５ 高誘電材テープ、１６ 実装基板、 １７セラミック基板、 １８、１９ インダクタンス。 1 BGA substrate, 2 semiconductor chip, 3 bump, 4 underfill resin, 5 ring adhesive, 6 heat spreader adhesive, 7 ring, 8 heat spreader, 9 semiconductor ball, 10 stacked via, 11 high dielectric constant layer, 11a high dielectric constant Capacitor by rate layer 11, 12 chip capacitor, 13 power supply / ground plane, 13a power supply plane, 13b ground plane, 14 high dielectric material adhesive, 15 high dielectric material tape, 16 mounting substrate, 17 ceramic substrate, 18, 19 inductance.

Claims (2)

有機材料を用いて形成された、多層構造のＢＧＡ基板、複数のバンプを介して前記ＢＧＡ基板の主面に接合された半導体チップ、及び前記主面と対向する前記ＢＧＡ基板の反対側の面であって、前記半導体チップのエッジ部分に対応する位置に形成され、電源とグランドとを接続するチップコンデンサを備えた半導体装置。   A BGA substrate having a multilayer structure formed using an organic material, a semiconductor chip bonded to the main surface of the BGA substrate through a plurality of bumps, and a surface opposite to the BGA substrate facing the main surface A semiconductor device comprising a chip capacitor formed at a position corresponding to an edge portion of the semiconductor chip and connecting a power source and a ground. 有機材料を用いて形成された、多層構造のＢＧＡ基板、複数のバンプを介して前記ＢＧＡ基板の主面に接合された半導体チップ、及び前記主面と対向する前記ＢＧＡ基板の反対側の面であって、前記半導体チップのエッジ部分に対応する位置に形成され、電源とグランドとを接続するチップコンデンサを備え、
前記ＢＧＡ基板は、前記多層構造の積層方向に重なるように複数の接続孔が繋ぎ合わされてなるスタックドビアを有し、
前記スタックドビアが形成されるピッチは、前記複数のバンプが形成されるピッチと一致している、半導体装置。 A BGA substrate having a multilayer structure formed using an organic material, a semiconductor chip bonded to the main surface of the BGA substrate through a plurality of bumps, and a surface opposite to the BGA substrate facing the main surface A chip capacitor formed at a position corresponding to the edge portion of the semiconductor chip and connecting a power source and a ground;
The BGA substrate has a stacked via formed by connecting a plurality of connection holes so as to overlap in the stacking direction of the multilayer structure,
The pitch at which the stacked vias are formed coincides with the pitch at which the plurality of bumps are formed.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07283538A (en) * 1994-04-14 1995-10-27 Ibiden Co Ltd Manufacture of multilayered printed wiring board
JPH08172252A (en) * 1994-12-19 1996-07-02 Kyocera Corp Circuit board
JPH09260537A (en) * 1996-03-26 1997-10-03 Sumitomo Kinzoku Electro Device:Kk Flip chip ceramic substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07283538A (en) * 1994-04-14 1995-10-27 Ibiden Co Ltd Manufacture of multilayered printed wiring board
JPH08172252A (en) * 1994-12-19 1996-07-02 Kyocera Corp Circuit board
JPH09260537A (en) * 1996-03-26 1997-10-03 Sumitomo Kinzoku Electro Device:Kk Flip chip ceramic substrate

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