JP4577228B2 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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JP4577228B2
JP4577228B2 JP2006032080A JP2006032080A JP4577228B2 JP 4577228 B2 JP4577228 B2 JP 4577228B2 JP 2006032080 A JP2006032080 A JP 2006032080A JP 2006032080 A JP2006032080 A JP 2006032080A JP 4577228 B2 JP4577228 B2 JP 4577228B2
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semiconductor chip
chip
semiconductor
bonding wire
conductor film
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JP2007214316A (ja
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義春 尾形
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Seiko Epson Corp
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Seiko Epson Corp
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Description

本発明は半導体装置および半導体装置の製造方法に関し、特に、半導体チップの積層構造に適用して好適なものである。
従来の半導体装置では、半導体チップの高密度実装を実現するために、フェースダウン実装された半導体チップ上にフェースアップ実装された半導体チップを積層する方法がある。
また、例えば、特許文献１には、積層された半導体チップ間のノイズによる干渉を抑制するために、第１半導体チップ上に搭載される第２半導体チップの裏面に導電体膜を形成する方法が開示されている。
特許第３６８１６９０号公報
しかしながら、従来の半導体チップの積層構造では、積層された半導体チップ間のノイズによる干渉が発生し、半導体装置の信頼性の低下を招くという問題があった。また、特許文献１に開示された方法では、第１半導体チップ上に搭載される第２半導体チップの裏面に導電体膜を形成する必要があり、第２半導体チップの製造工程の煩雑化を招くという問題があった。
そこで、本発明の目的は、チップ間のノイズによる干渉を抑制しつつ、チップを積層することが可能な半導体装置および半導体装置の製造方法を提供することである。
上述した課題を解決するために、本発明の一態様に係る半導体装置によれば、基材上にフェースダウン実装された第１半導体チップと、前記第１半導体チップ上にフェースアップ実装された第２半導体チップと、前記第１半導体チップと前記第２半導体チップとの間に挿入された電磁シールド板と、前記電磁シールド板に跨るようにして前記基材上にボンディングされたボンディングワイヤとを備えることを特徴とする。
これにより、第１半導体チップ上に第２半導体チップを積層した場合においても、第１半導体チップと第２半導体チップとの間のノイズによる干渉を抑制することが可能となるとともに、第１半導体チップまたは第２半導体チップの裏面に導電体膜を形成することなく、電磁シールド板をグランドに落とすことができる。このため、第１半導体チップおよび第２半導体チップの製造工程の煩雑化を招くことなく、第１半導体チップと第２半導体チップとの間の電磁シールド効果を高めることができ、コストアップを抑制しつつ、半導体チップの実装密度を向上させることができる。
また、本発明の一態様に係る半導体装置によれば、基材上にフェースダウン実装された第１半導体チップと、前記第１半導体チップ上に配置され、導電体膜が上面に形成されたダミーチップと、前記ダミーチップに跨るようにして前記導電体膜に接触し、前記基材上にボンディングされたボンディングワイヤと、前記ボンディングワイヤを介して前記ダミーチップ上にフェースアップ実装された第２半導体チップとを備えることを特徴とする。
これにより、第１半導体チップと第２半導体チップとの間にダミーチップを挟み込むことで、第１半導体チップと第２半導体チップとの間のノイズによる干渉を抑制することが可能となるとともに、第１半導体チップまたは第２半導体チップの裏面に導電体膜を形成することなく、ダミーチップの上面に形成された導電体膜をグランドに落とすことができる。このため、第１半導体チップおよび第２半導体チップの製造工程の煩雑化を招くことなく、第１半導体チップと第２半導体チップとの間の電磁シールド効果を高めることができ、コストアップを抑制しつつ、半導体チップの実装密度を向上させることができる。
また、本発明の一態様に係る半導体装置によれば、前記第２半導体チップ下に配置され、前記基材上に実装された電子部品とを備えることを特徴とする。
これにより、第２半導体チップと電子部品とを基材上に重ねて配置することができ、実装面積の増大を抑制することができる。
また、本発明の一態様に係る半導体装置によれば、前記第２半導体チップは前記第１半導体チップよりもサイズが大きいことを特徴とする。
これにより、第２半導体チップ下に配置された第１半導体チップと接触することなく、第２半導体チップ下に電子部品を配置することができ、実装面積の増大を抑制することができる。
また、本発明の一態様に係る半導体装置によれば、前記第１半導体チップにはアナログＩＣが形成され、前記第２半導体チップにはデジタルＩＣが形成されていることを特徴とする。
これにより、アナログＩＣとデジタルＩＣとを同一基材上に積層した場合においても、アナログＩＣとデジタルＩＣとの間のノイズによる干渉を抑制することが可能となり、実装面積の増大を抑制しつつ、アナログＩＣおよびデジタルＩＣの特性の劣化を低減することができる。
また、本発明の一態様に係る半導体装置の製造方法によれば、基材上に第１半導体チップをフェースダウン実装する工程と、導電体膜が上面に形成されたダミーチップを前記第１半導体チップ上に配置する工程と、前記ダミーチップに跨るようにして前記導電体膜に接触するボンディングワイヤを前記基材上にボンディングする工程と、前記ボンディングワイヤを介してダミーチップ上に第２半導体チップをフェースアップ実装する工程とを備えることを特徴とする。
これにより、第１半導体チップと第２半導体チップとの間にダミーチップを実装するとともに、ボンディング工程を追加することで、第１半導体チップと第２半導体チップとの間のノイズによる干渉を抑制することが可能となるとともに、ダミーチップの上面に形成された導電体膜をグランドに落とすことができ、コストアップを抑制しつつ、半導体チップの実装密度を向上させることができる。
また、本発明の一態様に係る半導体装置の製造方法によれば、前記ボンディングワイヤを前記基板上にボンディングする工程では、前記導電体膜と前記ボンディングワイヤとが接触しないようにボンディングし、前記第２の半導体チップを実装する工程において、前記第２の半導体チップで前記ボンディングワイヤを加圧し、前記ボンディングワイヤと前記導電体膜を接触させることを特徴とする。
以下、本発明の実施形態に係る半導体装置について図面を参照しながら説明する。
図１（ａ）は、本発明の一実施形態に係る半導体装置の概略構成を示す平面図、図１（ｂ）は、図１（ａ）のＡ−Ａ´線で切断した断面図である。
図１において、キャリア基板１の裏面にはランド２が設けられ、ランド２には突出電極３が形成されている。また、キャリア基板１の表面には、突出電極５を接合する端子電極４、ボンディングワイヤ１３、２１をそれぞれ接続する端子電極１５、１４、電子部品１７、１９をそれぞれ接続する端子電極１６、１８が設けられている。なお、キャリア基板１としては、例えば、両面基板、多層配線基板、ビルドアップ基板、テープ基板またはフィルム基板などを用いることができ、キャリア基板１の材質としては、例えば、ポリイミド樹脂、ガラスエポキシ樹脂、ＢＴレジン、アラミドとエポキシのコンポジットまたはセラミックなどを用いることができる。また、突出電極３としては、例えば、Ａｕバンプ、半田材などで被覆されたＣｕバンプやＮｉバンプ、あるいは半田ボールなどを用いることができる。
また、半導体チップ６には突出電極５が形成され、ダミーチップ８の上面には導電体膜９が形成され、半導体チップ１１には電極パッド１２が形成されている。なお、半導体チップ６としてアナログＩＣを搭載し、半導体チップ１１としてデジタルＩＣを搭載することができる。
ダミーチップ８としては、Ｓｉなどの半導体で構成されたベアチップを用いることができる。また、導電体膜９としては、例えば、ＡｌやＣｕなどの金属膜を用いることができ、導電体膜９の膜厚は１００００Å程度とすることができる。このとき、導電体膜９及びダミーチップ８は、次のようにして形成することができる。まず、Ｓｉなどの半導体で構成されたウエハーを用意する。このとき、ウエハーはダミーチップ８を複数形成できる大きさを持つものであってもよい。次に、このウエハーの一方の面の全面に、導電体膜９として、ＡｌやＣｕなどの金属膜を、スパッタリング法、ＣＶＤ（chemical vapor deposition）法、メッキ法などを用いて形成する。最後に、導電体膜９が形成されたウエハーをダミーチップ８として用いる大きさの個片に切断することで、導電体膜９及びダミーチップ８を形成することができる。なお、ウエハーを個片に切断する前に、ウエハーの裏面（導電体膜９が設けられた面とは反対側の面）の全面に接着層７を設けた後、ウエハーを個片に切断してもよい。
導電体膜９が設けられたダミーチップ８の代わりに、金属板やフェライト板などの電磁シールド板を用いるようにしてもよい。
そして、キャリア基板１上には、突出電極５を介して半導体チップ６がフェースアップ実装され、突出電極５は端子電極４に接合されている。なお、突出電極５と端子電極４とを接合する場合、例えば、半田接合や合金接合などの金属接合を用いるようにしてもよく、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＮＣＦ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合、ＮＣＰ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合などの圧接接合を用いるようにしてもよい。
さらに、半導体チップ６上には、導電体膜９が上面に形成されたダミーチップ８が接着層７を介して配置されている。接着層７とダミーチップ８は、平面図で見たときにほぼ同じ大きさであってもよい。言い換えると、接着層７の側面と、ダミーチップ８の側面が面一となるように形成されていてもよい。
導電体膜９上には、ダミーチップ８にアーチ状に跨るようにして端子電極１４にボンディングされたボンディングワイヤ２１が配されている。ボンディングワイヤ２１は、平面図で見たときに、間にダミーチップ８を挟む２つの端子電極１４上及び導電体膜９上に、連続的に設けられているといってもよい。そして、ボンディングワイヤ２１上には、接着層１０を介して半導体チップ１１がフェースアップ実装されている。なお、接着層１０と半導体チップ１１は、平面図で見たときにほぼ同じ大きさであってもよい。言い換えると、接着層１０の側面と半導体チップ１０の側面が面一となるように形成されていてもよい。
ボンディングワイヤ２１をダミーチップ８上に配する場合、ボンディングワイヤ２１上の半導体チップ１１が傾かないようにするために、複数のボンディングワイヤ２１を平行に配することが好ましい。ボンディングワイヤ２１及び半導体チップ１１は、例えば次のようにして形成することができる。まず、ボンディングワイヤ２１を、ダミーチップ８にアーチ状に跨るようにして、端子電極１４にボンディングする。このとき、ボンディングワイヤ２１が導電体膜９と接触するように形成してもよいが、ボンディングワイヤ２１は、導電体膜９と接触しないように（ボンディングワイヤ２１と導電体膜９との間に間隔が空くように）ボンディングされてもよい。次に、ダミーチップ８（及びボンディングワイヤ２１）上に半導体チップ１１を配置する。半導体チップ１１を配置する前に、ボンディングワイヤ２１が導電体膜９と接触していないときには、半導体チップ１１を配置するときに、半導体チップ１１でボンディングワイヤ２１を加圧し、ボンディングワイヤ２１と導電体膜９とを接触させてもよい。
半導体チップ１１に設けられた電極パッド１２はボンディングワイヤ１３を介して端子電極１５にボンディングされ、半導体チップ１１はボンディングワイヤ１３を介してキャリア基板１と電気的に接続されている。また、半導体チップ１１の側方には、端子電極１６を介して電子部品１７がキャリア基板１上に実装され、半導体チップ１１の下方には、端子電極１８を介して電子部品１９がキャリア基板１上に実装されている。なお、電子部品１９としては、例えば、抵抗やコンデンサやコイルやコネクタなどを用いることができる。そして、ボンディングワイヤ１３が接続された半導体チップ１１および電子部品１７、１９は、封止樹脂２０にて封止されている。
これにより、半導体チップ８上に半導体チップ１１を積層した場合においても、半導体チップ８、１１との間のノイズによる干渉を抑制することが可能となるとともに、半導体チップ８、１１の裏面に導電層を形成することなく、導電体膜９をグランドに落とすことができる。このため、半導体チップ８、１１の製造工程の煩雑化を招くことなく、半導体チップ８、１１間の電磁シールド効果を高めることができ、コストアップを抑制しつつ、半導体チップ８、１１の実装密度を向上させることができる。
なお、半導体チップ６、１１およびダミーチップ８は、半導体チップ６→ダミーチップ８→半導体チップ１１の順にサイズが大きくなるように構成することが好ましい。つまり、半導体チップ６よりダミーチップ８の方が大きく、ダミーチップ８より半導体チップ１１の方が大きくなるように構成することが好ましい。これにより、半導体チップ１１下に配置された半導体チップ６およびダミーチップ８と接触することなく、半導体チップ１１下に電子部品１９を配置することができ、実装面積の増大を抑制することができる。また、ダミーチップ８の厚さは、電子部品１９が半導体チップ１１に接触しないように設定することができる。つまり、導電体膜９の上面（導電体膜９のダミーチップ８と対向する面とは反対側の面）が、電子部品１９の上面（電子部品１９のキャリア基板１と対向する面とは反対側の面）よりも高くなるように、ダミーチップ８や導電体膜９の厚さを設定してもよい。これにより、電子部品１９が半導体チップ１１に接触することを防ぐことができ、ダミーチップ８をスペーサとしても用いることができ、製造工程の煩雑化を抑制しつつ、半導体チップ１１下に電子部品１９を配置することができる。
また、半導体チップ６、１１が実装されたキャリア基板１は、例えば、液晶表示装置、携帯電話、携帯情報端末、ビデオカメラ、デジタルカメラ、ＭＤ（Ｍｉｎｉ Ｄｉｓｃ）プレーヤ、ＩＣカード、ＩＣタグなどの電子機器に適用することができ、電子機器の小型・軽量化を可能としつつ、電子機器の信頼性を向上させることができる。
また、上述した実施形態では、半導体チップの実装方法を例にとって説明したが、本発明は、必ずしも半導体チップの実装方法に限定されることなく、例えば、抵抗やコンデンサやコネクタなどの実装方法の他、弾性表面波（ＳＡＷ）素子などのセラミック素子、光変調器や光スイッチなどの光学素子、磁気センサやバイオセンサなどの各種センサ類などの実装方法に適用してもよい。
本発明の一実施形態に係る半導体装置の概略構成を示す図。
符号の説明
１ キャリア基板、２ ランド、３、５ 突出電極、４、１４、１５、１６、１８ 端子電極、６、１１ 半導体チップ、７、１０ 接着層、８ ダミーチップ、９ 導電体膜、１２ 電極パッド、１３、２１ ボンディングワイヤ、１７、１９ 電子部品、２０ 封止樹脂

Claims (7)

  1. 基材上にフェースダウン実装された第１半導体チップと、
    前記第１半導体チップ上にフェースアップ実装された第２半導体チップと、
    前記第１半導体チップと前記第２半導体チップとの間に挿入された電磁シールド板と、
    前記電磁シールド板に跨るようにして前記基材上にボンディングされたボンディングワイヤとを備えることを特徴とする半導体装置。
  2. 基材上にフェースダウン実装された第１半導体チップと、
    前記第１半導体チップ上に配置され、導電体膜が上面に形成されたダミーチップと、
    前記ダミーチップに跨るようにして前記導電体膜に接触し、前記基材上にボンディングされたボンディングワイヤと、
    前記ボンディングワイヤを介して前記ダミーチップ上にフェースアップ実装された第２半導体チップとを備えることを特徴とする半導体装置。
  3. 前記第２半導体チップ下に配置され、前記基材上に実装された電子部品とを備えることを特徴とする請求項１または２記載の半導体装置。
  4. 前記第２半導体チップは前記第１半導体チップよりもサイズが大きいことを特徴とする請求項１から３のいずれか１項記載の半導体装置。
  5. 前記第１半導体チップにはアナログＩＣが形成され、前記第２半導体チップにはデジタルＩＣが形成されていることを特徴とする請求項１から４のいずれか１項記載の半導体装置。
  6. 基材上に第１半導体チップをフェースダウン実装する工程と、
    導電体膜が上面に形成されたダミーチップを前記第１半導体チップ上に配置する工程と、
    前記ダミーチップに跨るようにしてボンディングワイヤを前記基材上にボンディングする工程と、
    前記ボンディングワイヤを介してダミーチップ上に第２半導体チップをフェースアップ実装する工程とを備えることを特徴とする半導体装置の製造方法。
  7. 前記ボンディングワイヤを前記基板上にボンディングする工程では、前記導電体膜と前記ボンディングワイヤとが接触しないようにボンディングし、
    前記第２の半導体チップを実装する工程において、前記第２の半導体チップで前記ボンディングワイヤを加圧し、前記ボンディングワイヤと前記導電体膜を接触させることを特徴とする請求項６記載の半導体装置の製造方法。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI247371B (en) * 2004-02-06 2006-01-11 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
JP4876618B2 (ja) * 2006-02-21 2012-02-15 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
KR20090043898A (ko) * 2007-10-30 2009-05-07 삼성전자주식회사 스택 패키지 및 그 제조 방법, 및 스택 패키지를 포함하는카드 및 시스템
US7923846B2 (en) * 2007-11-16 2011-04-12 Stats Chippac Ltd. Integrated circuit package-in-package system with wire-in-film encapsulant
JP2011138879A (ja) * 2009-12-28 2011-07-14 Nec Toshiba Space Systems Ltd デバイス設置構造
JP6010880B2 (ja) * 2011-04-15 2016-10-19 株式会社ニコン 位置情報検出センサ、位置情報検出センサの製造方法、エンコーダ、モータ装置及びロボット装置
CN102820286A (zh) * 2012-07-16 2012-12-12 昆山华太电子技术有限公司 一种提高功率集成电路无源器件性能的结构
TWI747805B (zh) * 2014-10-08 2021-12-01 日商索尼半導體解決方案公司 攝像裝置及製造方法、以及電子機器
JP7103301B2 (ja) * 2018-08-03 2022-07-20 株式会社村田製作所 モジュール
US20200043864A1 (en) * 2018-08-03 2020-02-06 Murata Manufacturing Co., Ltd. Module
JP7036087B2 (ja) * 2018-08-03 2022-03-15 株式会社村田製作所 モジュール
US11355450B2 (en) 2019-08-01 2022-06-07 Mediatek Inc. Semiconductor package with EMI shielding structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269411A (ja) * 1999-03-17 2000-09-29 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2003229533A (ja) * 2002-02-01 2003-08-15 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
JP2004235310A (ja) * 2003-01-29 2004-08-19 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2005243754A (ja) * 2004-02-25 2005-09-08 Nec Electronics Corp 半導体装置
JP2005303056A (ja) * 2004-04-13 2005-10-27 Toshiba Corp 半導体集積回路装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111656A (ja) * 2002-09-18 2004-04-08 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP2006502596A (ja) * 2002-10-08 2006-01-19 チップパック，インク． 裏返しにされた第二のパッケージを有する積み重ねられた半導体マルチパッケージモジュール
JP2004296897A (ja) 2003-03-27 2004-10-21 Seiko Epson Corp 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
JP4123027B2 (ja) 2003-03-31 2008-07-23 セイコーエプソン株式会社 半導体装置の製造方法
JP3858854B2 (ja) * 2003-06-24 2006-12-20 富士通株式会社 積層型半導体装置
JP3722135B2 (ja) 2003-06-27 2005-11-30 セイコーエプソン株式会社 無線受信機およびｇｐｓ受信機
JP2005017198A (ja) 2003-06-27 2005-01-20 Seiko Epson Corp Ｇｐｓ受信機
JP3693057B2 (ja) 2003-07-04 2005-09-07 セイコーエプソン株式会社 半導体装置の製造方法
JP3835556B2 (ja) 2003-10-27 2006-10-18 セイコーエプソン株式会社 半導体装置の製造方法及び半導体装置の製造装置
JP4058642B2 (ja) 2004-08-23 2008-03-12 セイコーエプソン株式会社 半導体装置
KR100639701B1 (ko) * 2004-11-17 2006-10-30 삼성전자주식회사 멀티칩 패키지
JP4692720B2 (ja) 2004-12-17 2011-06-01 セイコーエプソン株式会社 配線基板、半導体装置及びその製造方法
JP4692719B2 (ja) 2004-12-17 2011-06-01 セイコーエプソン株式会社 配線基板、半導体装置及びその製造方法
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269411A (ja) * 1999-03-17 2000-09-29 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2003229533A (ja) * 2002-02-01 2003-08-15 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
JP2004235310A (ja) * 2003-01-29 2004-08-19 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2005243754A (ja) * 2004-02-25 2005-09-08 Nec Electronics Corp 半導体装置
JP2005303056A (ja) * 2004-04-13 2005-10-27 Toshiba Corp 半導体集積回路装置

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