JP2015026797A - 半導体装置 - Google Patents
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- 229910052814 silicon oxide Inorganic materials 0.000 description 2
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- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 238000001771 vacuum deposition Methods 0.000 description 1
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Abstract
【解決手段】第1導電型の第1半導体層と、前記第1半導体層に接して設けられた第1絶縁層と、前記第1絶縁層に接し前記第1半導体層内に設けられた第2導電型の第2半導体層と、前記第1絶縁層内に設けられ前記第1半導体層からの距離が異なる複数個の平坦なフィールドプレート電極が周期的に配置され、周期的に配置された前記フィールドプレート電極のうち、セル領域に最も近い1周期の前記フィールドプレート電極はエミッタ電極に接続されており、エミッタ電極に接続された前記フィールドプレート電極より外側の前記フィールドプレート電極はフローティングされている半導体装置。
【選択図】図1
Description
図1は第1の実施形態に係る半導体装置100の一例を示す平面図であり、IGBT(Insulated Gate Bipolar Transistor)素子が設けられるセル領域の外側に第1終端領域及び第2終端領域が設けられている。図2は図1のA−A’における断面の一部を示した図である。
以下に、図5を用いて第2の実施形態について説明する。なお、第2の実施形態について、第1の実施形態と同様の点については説明を省略し、異なる点について説明する。
以下に、図6を用いて第3の実施形態について説明する。なお、第3の実施形態について、第2の実施形態と同様の点については説明を省略し、異なる点について説明する。
以下に、第4の実施形態に係る半導体装置103について説明する。なお、第4の実施形態について、第3の実施形態と同様の点については説明を省略し、異なる点について説明する。図10は第4の実施形態に係る半導体装置103の構成の一例を示す縦断面図であり、IGBT素子が設けられるセル領域及びセル領域外側に位置する終端領域を示している。また、図10は図11及び図12のG−G’線における縦断面図である。
Claims (6)
- 第1導電型の第1半導体層と、
前記第1半導体層に接して設けられた第1絶縁層と、
前記第1絶縁層に接し前記第1半導体層内に設けられた第2導電型の第2半導体層と、
前記第1絶縁層内に設けられ前記第1半導体層からの距離が異なる複数個の平坦なフィールドプレート電極が周期的に配置され、
周期的に配置された前記フィールドプレート電極のうち、セル領域に最も近い1周期の前記フィールドプレート電極はエミッタ電極に接続されており、
エミッタ電極に接続された前記フィールドプレート電極より外側の前記フィールドプレート電極はフローティングされている半導体装置。 - 第1導電型の第1半導体層と、
前記第1半導体層に接して設けられた第1絶縁層と、
前記第1絶縁層に接し前記第1半導体層内に設けられた第2導電型の第2半導体層と、
前記第1絶縁層内に設けられ前記第1半導体層からの距離が異なる複数個の平坦なフィールドプレート電極が周期的に配置され、
前記フィールドプレート電極のうち、少なくとも1個は前記第1絶縁層に凹部を形成し、電極を埋め込むことで形成する半導体装置。 - 前記フィールドプレート電極のうち、第1半導体層からの距離が同じ複数個の平坦なフィールドプレート電極を持つ請求項1または2に記載の半導体装置。
- 前記第1絶縁層に接し前記第1半導体層内に設けられた第2導電型の第3半導体層と、
前記第1絶縁層に接し前記第3半導体層内に選択的に設けられた第1導電型の第4半導体層と、
前記第3半導体層及び前記第4半導体層に接し前記第1絶縁層内に設けられた第2接続層と、
前記第2接続層に接し前記第1絶縁層内に設けられ第1の方向に延在した第1配線層と、
前記第1配線層に接し前記第1絶縁層内に設けられ前記第1の方向とは異なる第2の方向に延在した第2配線層と、
前記第1配線層と前記エミッタ電極に接し前記第1の方向に延在した第1接続層と、
前記第2配線層に接し前記第2の方向に延在した第3接続層と、
を備え、前記第1の方向及び前記第2の方向を含む面で切断した前記第1配線層及び前記第2配線層の断面積が前記第2接続層の断面積より大きく、前記第1の方向及び前記第2の方向を含む面で切断した前記第1接続層及び前記第3接続層の断面積が前記第2接続層の断面積より大きい請求項1から3に記載の半導体装置。 - 前記第1配線層及び前記第2配線層は、前記フィールドプレート電極のうち、少なくとも1個のフィールドプレート電極と前記第1半導体層からの距離が略同じである請求項4に記載の半導体装置。
- 前記フィールドプレート電極のうち、少なくとも一部は互いに交差し、接している請求項5に記載の半導体装置。
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JP2013205884A JP6101183B2 (ja) | 2013-06-20 | 2013-09-30 | 半導体装置 |
CN201410071801.7A CN104241347B (zh) | 2013-06-20 | 2014-02-28 | 半导体装置 |
US14/195,784 US9653557B2 (en) | 2013-06-20 | 2014-03-03 | Semiconductor device |
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JP2017168659A (ja) * | 2016-03-16 | 2017-09-21 | 富士電機株式会社 | 半導体装置および製造方法 |
US10347713B2 (en) | 2017-09-15 | 2019-07-09 | Kabushiki Kaisha Toshiba | Semiconductor device having a triple region resurf structure |
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JP2016174040A (ja) | 2015-03-16 | 2016-09-29 | 株式会社東芝 | 半導体装置 |
CN104882382B (zh) * | 2015-05-19 | 2018-01-12 | 上海先进半导体制造股份有限公司 | Mosfet终端结构及其制造方法 |
KR101872069B1 (ko) * | 2015-05-22 | 2018-06-28 | 매그나칩 반도체 유한회사 | 플로팅 구조를 갖는 쇼트키 다이오드 |
US9806186B2 (en) * | 2015-10-02 | 2017-10-31 | D3 Semiconductor LLC | Termination region architecture for vertical power transistors |
JP6987015B2 (ja) * | 2018-04-26 | 2021-12-22 | 三菱電機株式会社 | 半導体装置 |
CN114467165A (zh) * | 2019-10-08 | 2022-05-10 | 三菱电机株式会社 | 半导体装置 |
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US10347713B2 (en) | 2017-09-15 | 2019-07-09 | Kabushiki Kaisha Toshiba | Semiconductor device having a triple region resurf structure |
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CN104241347A (zh) | 2014-12-24 |
US9653557B2 (en) | 2017-05-16 |
JP6101183B2 (ja) | 2017-03-22 |
US20140374791A1 (en) | 2014-12-25 |
CN104241347B (zh) | 2017-10-31 |
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