JP2012256844A - 積層チップパッケージおよびその製造方法 - Google Patents
積層チップパッケージおよびその製造方法 Download PDFInfo
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- JP2012256844A JP2012256844A JP2012034811A JP2012034811A JP2012256844A JP 2012256844 A JP2012256844 A JP 2012256844A JP 2012034811 A JP2012034811 A JP 2012034811A JP 2012034811 A JP2012034811 A JP 2012034811A JP 2012256844 A JP2012256844 A JP 2012256844A
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Abstract
【解決手段】積層チップパッケージ1は、本体2と配線3を備えている。本体2は、積層された複数の階層部分10を含む主要部分2Mを有している。各階層部分10は、第1の面とその反対側の第2の面とを有する半導体チップと、複数の電極を含んでいる。複数の電極は、半導体チップの第1の面側に配置されている。複数の階層部分10は、半導体チップの第1の面同士または第2の面同士が対向するように配置された第1および第2の階層部分の対を2つ以上含んでいる。複数の電極は、複数の第1の接続部と複数の第2の接続部を含んでいる。第1の階層部分では複数の第1の接続部が複数のラインに接し、第2の階層部分では複数の第2の接続部が複数のラインに接している。
【選択図】図1
Description
すなわち、積層基礎構造物を作製する工程は、
それぞれ、互いに反対側を向いた第1および第2の面を有する半導体ウェハにおける第1の面に処理を施すことによって、各々が半導体チップとなる予定の、配列された複数の半導体チップ予定部を含み、且つ半導体ウェハの第1および第2の面に対応する第1および第2の面を有する第1ないし第4の研磨前基礎構造物を作製する工程と、
第1の研磨前基礎構造物の第1の面と第2の研磨前基礎構造物の第1の面とが対向するように、第1の研磨前基礎構造物と第2の研磨前基礎構造物とを張り合わせて、第1の研磨前積層体を形成する工程と、
第2の研磨前基礎構造物が第2の基礎構造物になり、第1の研磨前基礎構造物と第2の基礎構造物とを含む第1の積層体が形成されるように、第1の研磨前積層体における第2の研磨前基礎構造物の第2の面を研磨する工程と、
第3の研磨前基礎構造物の第1の面と第4の研磨前基礎構造物の第1の面とが対向するように、第3の研磨前基礎構造物と第4の研磨前基礎構造物とを張り合わせて、第2の研磨前積層体を形成する工程と、
第3の研磨前基礎構造物が第3の基礎構造物になり、第3の基礎構造物と第4の研磨前基礎構造物とを含む第2の積層体が形成されるように、第2の研磨前積層体における第3の研磨前基礎構造物の第2の面を研磨する工程と、
第2の基礎構造物と第3の基礎構造物とが対向するように、第1の積層体と第2の積層体を張り合わせて、第3の研磨前積層体を形成する工程と、
第4の研磨前基礎構造物が第4の基礎構造物になり、第3の研磨前積層体が第3の積層体になるように、第3の研磨前積層体における第4の研磨前基礎構造物の第2の面を研磨する工程と、
第1の研磨前基礎構造物が第1の基礎構造物になるように、第3の積層体における第1の研磨前基礎構造物の第2の面を研磨する工程とを含んでいてもよい。
以下、本発明の実施の形態について図面を参照して詳細に説明する。始めに、図1ないし図5を参照して、本発明の第1の実施の形態に係る積層チップパッケージの構成について説明する。図1は、本実施の形態に係る積層チップパッケージの斜視図である。図2は、下側から見た図1の積層チップパッケージを示す斜視図である。図3は、図1に示した積層チップパッケージに含まれる1つの階層部分を示す平面図である。図4は、図3に示した階層部分を示す斜視図である。図5は、図1に示した積層チップパッケージに含まれる第1および第2の階層部分の対を分解して示す斜視図である。
次に、本発明の第2の実施の形態について説明する。始めに、図31ないし図35を参照して、本実施の形態に係る積層チップパッケージの構成について説明する。図31は、本実施の形態に係る積層チップパッケージの斜視図である。図32は、下側から見た図31の積層チップパッケージを示す斜視図である。図33は、図31に示した積層チップパッケージに含まれる1つの階層部分を示す平面図である。図34は、図33に示した階層部分を示す斜視図である。図35は、図31に示した積層チップパッケージに含まれる第1および第2の階層部分の対を分解して示す斜視図である。
次に、本発明の第3の実施に係る積層チップパッケージの製造方法について説明する。本実施の形態に係る積層チップパッケージの構成は、第2の実施の形態と同じである。本実施の形態に係る積層チップパッケージの製造方法では、積層基礎構造物を作製する工程のうち、図36に示した2つの研磨前基礎構造物109を含む研磨前積層体を形成した後の工程が、第2の実施の形態と異なっている。
Claims (10)
- 本体と、配線とを備え、
前記本体は、積層された複数の階層部分を含むと共に上面と下面を有する主要部分を有し、
前記配線は、複数の階層部分の全てを経由する複数のラインを含み、
前記複数の階層部分の各々は、第1の面とその反対側の第2の面とを有する半導体チップと、複数の電極とを含み、
前記複数の電極は、前記半導体チップの前記第1の面側に配置され、
前記複数の階層部分は、前記半導体チップの第1の面同士または第2の面同士が対向するように配置された第1および第2の階層部分の対を2つ以上含み、
前記第1および第2の階層部分における前記複数の電極のレイアウトは同じであり、
前記複数の電極は、複数の第1の接続部と複数の第2の接続部とを含み、
前記第1の階層部分では、前記複数の第1の接続部が前記複数のラインに接し、前記第2の階層部分では、前記複数の第2の接続部が前記複数のラインに接していることを特徴とする積層チップパッケージ。 - 前記本体は、上面、下面および第1ないし第4の側面を有し、
前記複数のラインは、前記本体の第1の側面に配置された複数のワイヤであり、
前記第1の階層部分では、前記複数の第1の接続部が前記第1の側面に配置されて前記複数のワイヤに接し、前記第2の階層部分では、前記複数の第2の接続部が前記第1の側面に配置されて前記複数のワイヤに接していることを特徴とする請求項1記載の積層チップパッケージ。 - 前記本体は、更に、前記主要部分の上面に配置されて前記複数のラインに電気的に接続された複数の第1の端子と、前記主要部分の下面に配置されて前記複数のラインに電気的に接続された複数の第2の端子とを有し、
前記2つ以上の第1および第2の階層部分の対は、いずれも、前記半導体チップの第2の面同士が対向するように配置されたものであり、
前記第1の端子は、前記主要部分の上面に最も近い1つの階層部分における前記複数の電極を用いて構成され、
前記第2の端子は、前記主要部分の下面に最も近い1つの階層部分における前記複数の電極を用いて構成されていることを特徴とする請求項1記載の積層チップパッケージ。 - 前記複数のラインは、前記主要部分内の全ての階層部分に共通する用途を有する複数の共通ラインと、互いに異なる階層部分によって利用される複数の階層依存ラインとを含み、
前記複数の電極は、前記複数の共通ラインに電気的に接続された複数の共通電極と、前記複数の階層依存ラインのうち、その階層部分が利用する階層依存ラインにのみ選択的に、電気的に接続された選択的接続電極とを含み、
前記複数の階層部分のうちの少なくとも1つにおいて、前記複数の共通電極および前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記複数の共通ラインおよび前記階層依存ラインに電気的に接続されていることを特徴とする請求項1記載の積層チップパッケージ。 - 前記半導体チップは、複数のメモリセルを含むことを特徴とする請求項1記載の積層チップパッケージ。
- 請求項1記載の積層チップパッケージを複数個製造する方法であって、
各々が前記主要部分に含まれる階層部分のいずれかとなる予定の、配列された複数の予備階層部分を含み、後に隣接する予備階層部分の境界位置で切断される複数の基礎構造物を積層して、積層基礎構造物を作製する工程と、
前記積層基礎構造物を用いて、前記積層チップパッケージを複数個作製する工程とを備え、
前記複数の基礎構造物の各々は、前記半導体チップの第1および第2の面に対応する第1および第2の面を有し、
前記積層基礎構造物を作製する工程は、2つの基礎構造物の第1の面同士または第2の面同士が対向するように配置された基礎構造物の対を2つ以上含むように前記積層基礎構造物を作製することを特徴とする積層チップパッケージの製造方法。 - 前記2つ以上の第1および第2の階層部分の対は、いずれも、前記半導体チップの第2の面同士が対向するように配置されたものであり、
前記積層基礎構造物を作製する工程は、
それぞれ、互いに反対側を向いた第1および第2の面を有する半導体ウェハにおける前記第1の面に処理を施すことによって、各々が前記半導体チップとなる予定の、配列された複数の半導体チップ予定部を含み、且つ前記半導体ウェハの第1および第2の面に対応する第1および第2の面を有する第1および第2の研磨前基礎構造物を作製する工程と、
前記第1および第2の研磨前基礎構造物を、それらの第1の面に板状の治具が張り付けられた状態でそれらの第2の面を研磨して、第1および第2の基礎構造物を形成する工程と、
それぞれ第1の面に前記治具が張り付けられた状態の前記第1および第2の基礎構造物を、それらの第2の面同士が対向するように張り合わせて、基礎構造物の対を形成する工程と、
前記基礎構造物の対を2つ以上張り合わせて、前記積層基礎構造物を形成する工程とを含むことを特徴とする請求項6記載の積層チップパッケージの製造方法。 - 前記2つ以上の第1および第2の階層部分の対は、いずれも、前記半導体チップの第1の面同士が対向するように配置されたものであり、
前記積層基礎構造物を作製する工程は、
それぞれ、互いに反対側を向いた第1および第2の面を有する半導体ウェハにおける前記第1の面に処理を施すことによって、各々が前記半導体チップとなる予定の、配列された複数の半導体チップ予定部を含み、且つ前記半導体ウェハの第1および第2の面に対応する第1および第2の面を有する第1および第2の研磨前基礎構造物を作製する工程と、
前記第1および第2の研磨前基礎構造物を、それらの第1の面同士が対向するように張り合わせて、研磨前積層体を形成する工程と、
前記研磨前積層体における前記第1および第2の研磨前基礎構造物のそれぞれの第2の面を研磨して、基礎構造物の対を形成する工程と、
前記基礎構造物の対を2つ以上張り合わせて、前記積層基礎構造物を形成する工程とを含むことを特徴とする請求項6記載の積層チップパッケージの製造方法。 - 前記2つ以上の第1および第2の階層部分の対は、いずれも、前記半導体チップの第1の面同士が対向するように配置されたものであり、
前記積層基礎構造物を作製する工程は、
それぞれ、互いに反対側を向いた第1および第2の面を有する半導体ウェハにおける前記第1の面に処理を施すことによって、各々が前記半導体チップとなる予定の、配列された複数の半導体チップ予定部を含み、且つ前記半導体ウェハの第1および第2の面に対応する第1および第2の面を有する第1ないし第4の研磨前基礎構造物を作製する工程と、
前記第1の研磨前基礎構造物の第1の面と前記第2の研磨前基礎構造物の第1の面とが対向するように、前記第1の研磨前基礎構造物と前記第2の研磨前基礎構造物とを張り合わせて、第1の研磨前積層体を形成する工程と、
前記第2の研磨前基礎構造物が前記第2の基礎構造物になり、前記第1の研磨前基礎構造物と前記第2の基礎構造物とを含む第1の積層体が形成されるように、前記第1の研磨前積層体における前記第2の研磨前基礎構造物の第2の面を研磨する工程と、
前記第3の研磨前基礎構造物の第1の面と前記第4の研磨前基礎構造物の第1の面とが対向するように、前記第3の研磨前基礎構造物と前記第4の研磨前基礎構造物とを張り合わせて、第2の研磨前積層体を形成する工程と、
前記第3の研磨前基礎構造物が前記第3の基礎構造物になり、前記第3の基礎構造物と前記第4の研磨前基礎構造物とを含む第2の積層体が形成されるように、前記第2の研磨前積層体における前記第3の研磨前基礎構造物の第2の面を研磨する工程と、
前記第2の基礎構造物と前記第3の基礎構造物とが対向するように、前記第1の積層体と第2の積層体を張り合わせて、第3の研磨前積層体を形成する工程と、
前記第4の研磨前基礎構造物が前記第4の基礎構造物になり、前記第3の研磨前積層体が第3の積層体になるように、前記第3の研磨前積層体における前記第4の研磨前基礎構造物の第2の面を研磨する工程と、
前記第1の研磨前基礎構造物が前記第1の基礎構造物になるように、前記第3の積層体における前記第1の研磨前基礎構造物の第2の面を研磨する工程とを含むことを特徴とする請求項6記載の積層チップパッケージの製造方法。 - 前記積層基礎構造物を作製する工程は、更に、それぞれ前記第1ないし第4の研磨前基礎構造物を作製する工程から前記第3の研磨前積層体における前記第4の研磨前基礎構造物の第2の面を研磨する工程までの一連の工程を経て形成された2つの第3の積層体を、前記第4の基礎構造物同士が対向するように張り合わせる工程を含み、
前記第3の積層体における前記第1の研磨前基礎構造物の第2の面を研磨する工程は、張り合わされた前記2つの第3の積層体の各々について行われ、これにより、積層された第1ないし第4の基礎構造物を2組含む積層基礎構造物が作製されることを特徴とする請求項9記載の積層チップパッケージの製造方法。
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