JP2010515259A - 積重ねパッケージ - Google Patents
積重ねパッケージ Download PDFInfo
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- JP2010515259A JP2010515259A JP2009544043A JP2009544043A JP2010515259A JP 2010515259 A JP2010515259 A JP 2010515259A JP 2009544043 A JP2009544043 A JP 2009544043A JP 2009544043 A JP2009544043 A JP 2009544043A JP 2010515259 A JP2010515259 A JP 2010515259A
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Abstract
Description
この国際特許出願は、2006年12月28日に出願された米国特許出願第11/648,172号からの優先権を主張する。
本発明は全体的に、積重ね超小型電子パッケージに関し、より詳細には、ウェハ・レベルで製造された積重ね超小型電子パッケージ及びそのようなパッケージを作る方法に関する。
Claims (19)
- 第1の裏面を有する第1の超小型電子素子と、
第2の裏面を有し、前記第1の超小型電子素子に装着されて積重ねパッケージを形成する第2の超小型電子素子と、
少なくとも1つのブリッジング素子と
を備えており、
前記第1の超小型電子素子の前記第1の裏面は、前記第2の超小型電子素子の前記第2の裏面と向き合っており、
前記第1の超小型電子素子及び前記第2の超小型電子素子は、前面と該前面に配置された複数の接点をそれぞれ有し、前記少なくとも1つのブリッジング素子は、前記第1の超小型電子素子の前記複数の接点と前記第2の超小型電子素子の前記複数の接点との間に延びて、前記第1の超小型電子素子と前記第2の超小型電子素子とを電気的に接続することを特徴とする、超小型電子構造体。 - 前記第1の超小型電子素子が、前記前面から前記第1の超小型電子素子の前記裏面に延びる第1の端部と第2の端部とを備えて、前記少なくとも1つのブリッジング素子が前記第1の端部と前記第2の端部の外側に配置されることを特徴とする請求項1に記載の超小型電子構造体。
- 前記第1の超小型電子素子と前記第2の超小型電子素子の前記それぞれの前面上に配置された複数のトレースをさらに具備し、前記複数のトレースの少なくとも幾つかが、前記第1の超小型電子素子上の前記複数の接点の少なくとも幾つかから、前記少なくとも1つのブリッジング素子まで延び、前記複数のトレースの少なくとも幾つかが、前記第2の超小型電子素子の前記複数の接点の少なくとも幾つかから前記少なくとも1つのブリッジング素子まで延びることを特徴とする請求項2に記載の超小型電子構造体。
- 前記第1の超小型電子素子を前記第2の超小型電子素子に固着させる接着剤をさらに備えることを特徴とする請求項3に記載の超小型電子構造体。
- 前記第1の超小型電子素子が、第1の端部と第2の端部を具備し、前記少なくとも1つのブリッジング素子が、前記第1の端部と前記第2の端部との間に配置されることを特徴とする請求項1に記載の超小型電子構造体。
- 前記第2の超小型電子素子が第1の端部と第2の端部を有し、前記少なくとも1つのブリッジング素子が前記第2の超小型電子素子の前記第1の端部と前記第2の端部との間に配置されることを特徴とする請求項5に記載の超小型電子構造体。
- 前記第1の超小型電子素子が、前記前面から前記裏面に延びる複数のバイアを備えており、前記少なくとも1つのブリッジング素子が前記複数のバイアの少なくとも1つの中に配置されることを特徴とする請求項6に記載の超小型電子構造体。
- 前面と裏面を有する第3の超小型電子素子、及び裏面を有する第4の超小型電子素子をさらに具備し、前記第3及び第4の超小型電子素子が、前記第3の超小型電子素子の裏面が前記第4の超小型電子素子の裏面を向くように装着され、前記第3の超小型電子素子が、前記第3の超小型電子素子の前面が前記第2の超小型電子素子の前面を向くように前記第2の超小型電子素子にも装着されることを特徴とする請求項1に記載の超小型電子構造体。
- 積重ね形超小型電子素子を組み立てる方法であって、
複数の超小型電子素子を含む第1のサブアセンブリを、複数の超小型電子素子を含む第2のサブアセンブリ上に積み重ねることによって、超小型電子構造体を形成するステップと、
前記第1のサブアセンブリの前面に配置された複数の接点を、前記第2のサブアセンブリの前面に配置された複数の接点に電気的に接続するステップと
を含んでおり、
前記第1のサブアセンブリと前記第2のサブアセンブリの裏面が、互いに向き合っていることを特徴とする方法。 - 前記第1のサブアセンブリ及び前記第2のサブアセンブリはそれぞれ、前記超小型電子構造体を形成するステップの間は整列されているソー・レーンを備えることができることを特徴とする請求項9に記載の方法。
- 個々の積重ねユニットを形成するために、前記第1及び第2のサブアセンブリのソー・レーンを通ってダイスカットするステップをさらに含み、前記第1のサブアセンブリと前記第2のサブアセンブリの前記複数の超小型電子素子の少なくとも幾つかが、前記ダイスカットするステップの後でトレースが配置されるように、それぞれの接点から前記それぞれ第1及び第2のサブアセンブリの前記ソー・レーンまで延びるトレースを有することを特徴とする請求項10に記載の方法。
- 前記第1のサブアセンブリの複数の接点を、前記第2のサブアセンブリの接点に電気的に接続するステップが、前記第1のサブアセンブリと前記第2のサブアセンブリのトレースの間にブリッジング素子を形成するステップを含むことを特徴とする請求項11に記載の方法。
- 前記ブリッジング素子が、前記第1のサブアセンブリと前記第2のサブアセンブリの両方の前記超小型電子素子の端部に配置されることを特徴とする請求項12に記載の方法。
- 請求項12に基づいて第1の個別の積重ねユニットと第2の個別の積重ねユニットを形成するステップを含む積重ねパッケージを組み立てる方法が、第1の個別の積重ねユニットの接点の少なくとも幾つかを第2の個別の積重ねユニットの接点の少なくとも幾つかに電気的に接続するステップをさらに含むことを特徴とする方法。
- 前記第1のサブアセンブリと前記第2のサブアセンブリの両方の中に複数のバイアを形成するステップをさらに含み、前記複数のバイアが前記第1及び第2のサブアセンブリの裏面から前記両方のサブアセンブリの前面に延び、前記第1及び第2のサブアセンブリの接点と整列されて、前記それぞれのサブアセンブリの前記裏面に前記接点を露出させることを特徴とする請求項9に記載の方法。
- 導電性材料が前記複数のトレースの中に配置されることを特徴とする請求項15に記載の方法。
- 前記超小型電子構造体を形成するステップの前に、前記第1のサブアセンブリの複数のバイア内の導電性材料が、前記第2のサブアセンブリの複数のバイア内の導電性材料と整列されることを特徴とする請求項16に記載の方法。
- 前記第1のサブアセンブリの接点を前記第2のサブアセンブリの接点に電気的に接続するステップが、前記第1のサブアセンブリの複数のバイア内に配置された前記導電性材料を、前記第2のサブアセンブリの複数のバイア内の前記導電性材料に電気的に接続するステップを含むことを特徴とする請求項17に記載の方法。
- 個別の積重ねユニットを形成するために、前記超小型電子構造体を所定の位置でダイスカットするステップをさらに含むことを特徴とする請求項18に記載の方法。
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JP5567346B2 (ja) | 2014-08-06 |
US8349654B2 (en) | 2013-01-08 |
CN101595562A (zh) | 2009-12-02 |
US20110230013A1 (en) | 2011-09-22 |
EP2097925B1 (en) | 2020-11-04 |
WO2008085391A3 (en) | 2008-09-12 |
US7952195B2 (en) | 2011-05-31 |
KR20090128376A (ko) | 2009-12-15 |
EP2097925A2 (en) | 2009-09-09 |
CN101595562B (zh) | 2011-09-21 |
KR101454332B1 (ko) | 2014-10-23 |
US20080157323A1 (en) | 2008-07-03 |
WO2008085391A2 (en) | 2008-07-17 |
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