JP5154667B2 - 積層チップパッケージおよびその製造方法 - Google Patents
積層チップパッケージおよびその製造方法 Download PDFInfo
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- JP5154667B2 JP5154667B2 JP2011010371A JP2011010371A JP5154667B2 JP 5154667 B2 JP5154667 B2 JP 5154667B2 JP 2011010371 A JP2011010371 A JP 2011010371A JP 2011010371 A JP2011010371 A JP 2011010371A JP 5154667 B2 JP5154667 B2 JP 5154667B2
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Description
それぞれ半導体チップとなる予定の、配列された複数の半導体チップ予定部を含む基礎構造物前ウェハを作製する工程と、
基礎構造物前ウェハに含まれる複数の半導体チップ予定部について、正常に動作する半導体チップ予定部と正常に動作しない半導体チップ予定部とを判別する工程と、
基礎構造物前ウェハが基礎構造物になるように、正常に動作する半導体チップ予定部では複数の第1の電極が半導体チップ予定部に接触してこれに電気的に接続され、正常に動作しない半導体チップ予定部では複数の第1の電極が半導体チップ予定部に接触しないように、複数の第1の電極を形成する工程とを含んでいてもよい。
以下、本発明の実施の形態について図面を参照して詳細に説明する。始めに、図1ないし図5を参照して、本発明の第1の実施の形態に係る積層チップパッケージの構成について説明する。図1は、本発明の第1の実施の形態に係る積層チップパッケージの斜視図である。図2は、下側から見た図1の積層チップパッケージを示す斜視図である。図3は、図1の積層チップパッケージの配線を除いた部分を示す斜視図である。図4は、図1に示した積層チップパッケージに含まれる1つの階層部分を示す平面図である。図5は、図4に示した階層部分を示す斜視図である。
次に、本発明の第2の実施の形態について説明する。始めに、図50ないし図54を参照して、本実施の形態に係る積層チップパッケージ1について説明する。図50は、本実施の形態に係る積層チップパッケージ1の斜視図である。図51は、下側から見た図50の積層チップパッケージ1を示す斜視図である。図52は、図50の積層チップパッケージ1の配線を除いた部分を示す斜視図である。図53は、図50に示した積層チップパッケージ1に含まれる1つの階層部分を示す平面図である。図54は、図53に示した階層部分を示す斜視図である。
Claims (17)
- 上面、下面および4つの側面を有する本体と、
前記本体の少なくとも1つの側面に配置された複数のワイヤを含む配線とを備えた積層チップパッケージであって、
前記本体は、積層された複数の階層部分を含むと共に上面と下面を有する主要部分と、前記主要部分の上面と下面のうちの少なくとも上面に配置されて前記複数のワイヤに電気的に接続された複数の端子とを有し、
前記複数の階層部分の各々は、半導体チップと、前記複数のワイヤに電気的に接続された複数の電極とを含み、
前記複数の端子は、前記主要部分の上面に配置されて前記複数のワイヤに電気的に接続された複数の第1の端子を含み、
前記複数の第1の端子は、最も上に位置する階層部分における前記複数の電極を用いて構成され、
前記複数の電極は、前記半導体チップとの電気的接続のための複数の第1の電極と、前記半導体チップに接触しない複数の第2の電極とを含み、
前記複数の階層部分のうちの少なくとも1つにおいて、前記複数の第1の電極は、前記半導体チップに接触してこれに電気的に接続され、
前記複数のワイヤは、前記主要部分内の全ての階層部分に共通する用途を有する複数の共通ワイヤと、互いに異なる階層部分によって利用される複数の階層依存ワイヤとを含み、
前記複数の第1の電極は、前記複数の共通ワイヤに電気的に接続され、
前記複数の第2の電極は、前記複数の階層依存ワイヤに電気的に接続され、
前記複数の階層部分の各々は、更に、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続された選択的接続電極を含み、
前記複数の階層部分のうちの少なくとも1つにおいて、前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記階層依存ワイヤに電気的に接続されていることを特徴とする積層チップパッケージ。 - 前記複数の端子は、更に、前記主要部分の下面に配置されて前記複数のワイヤに電気的に接続された複数の第2の端子を含むことを特徴とする請求項1記載の積層チップパッケージ。
- 前記半導体チップは、複数のメモリセルを含むことを特徴とする請求項1記載の積層チップパッケージ。
- 前記半導体チップは、4つの側面を有し、
前記階層部分は、更に、前記半導体チップの4つの側面のうちの少なくとも1つの側面を覆う絶縁部を含み、
前記絶縁部は、前記複数のワイヤが配置された前記本体の前記少なくとも1つの側面に配置された少なくとも1つの端面を有することを特徴とする請求項1記載の積層チップパッケージ。 - 前記複数の階層部分は、少なくとも1つの第1の種類の階層部分と、少なくとも1つの第2の種類の階層部分とを含み、
前記第1の種類の階層部分では、前記複数の第1の電極は、前記半導体チップに接触してこれに電気的に接続され、
前記第2の種類の階層部分では、前記複数の第1の電極は、前記半導体チップに接触しておらず、
前記第1の種類の階層部分では、前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記階層依存ワイヤに電気的に接続され、
前記第2の種類の階層部分では、前記選択的接続電極が前記半導体チップに電気的に接続されていないことによって、前記半導体チップが前記階層依存ワイヤに電気的に接続されていないことを特徴とする請求項1記載の積層チップパッケージ。 - 前記第1の種類の階層部分における前記半導体チップは正常に動作するものであり、前記第2の種類の階層部分における前記半導体チップは正常に動作しないものであることを特徴とする請求項5記載の積層チップパッケージ。
- 請求項1記載の積層チップパッケージを複数個製造する方法であって、
各々が前記主要部分に含まれる階層部分のいずれかとなる予定の、配列された複数の予備階層部分を含み、後に隣接する予備階層部分の境界位置で切断される複数の基礎構造物を積層して、積層基礎構造物を作製する工程と、
前記積層基礎構造物を用いて、前記積層チップパッケージを複数個作製する工程とを備えたことを特徴とする積層チップパッケージの製造方法。 - 前記複数の階層部分は、少なくとも1つの第1の種類の階層部分と、少なくとも1つの第2の種類の階層部分とを含み、
前記第1の種類の階層部分では、前記複数の第1の電極は、前記半導体チップに接触してこれに電気的に接続され、
前記第2の種類の階層部分では、前記複数の第1の電極は、前記半導体チップに接触しておらず、
前記第1の種類の階層部分では、前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記階層依存ワイヤに電気的に接続され、
前記第2の種類の階層部分では、前記選択的接続電極が前記半導体チップに電気的に接続されていないことによって、前記半導体チップが前記階層依存ワイヤに電気的に接続されていないことを特徴とする請求項7記載の積層チップパッケージの製造方法。 - 前記第1の種類の階層部分における前記半導体チップは正常に動作するものであり、前記第2の種類の階層部分における前記半導体チップは正常に動作しないものであることを特徴とする請求項8記載の積層チップパッケージの製造方法。
- 前記積層基礎構造物を作製する工程は、各基礎構造物を作製するための一連の工程として、
それぞれ前記半導体チップとなる予定の、配列された複数の半導体チップ予定部を含む基礎構造物前ウェハを作製する工程と、
前記基礎構造物前ウェハに含まれる複数の半導体チップ予定部について、正常に動作する半導体チップ予定部と正常に動作しない半導体チップ予定部とを判別する工程と、
前記基礎構造物前ウェハが前記基礎構造物になるように、正常に動作する半導体チップ予定部では前記複数の第1の電極が前記半導体チップ予定部に接触してこれに電気的に接続され、正常に動作しない半導体チップ予定部では前記複数の第1の電極が前記半導体チップ予定部に接触しないように、前記複数の第1の電極を形成する工程とを含むことを特徴とする請求項9記載の積層チップパッケージの製造方法。 - 前記積層基礎構造物を作製する工程は、各基礎構造物を作製するための一連の工程として、更に、正常に動作する半導体チップ予定部では前記選択的接続電極が前記半導体チップ予定部に電気的に接続され、正常に動作しない半導体チップ予定部では前記選択的接続電極が前記半導体チップ予定部に電気的に接続されないように、前記選択的接続電極を形成する工程を含むことを特徴とする請求項10記載の積層チップパッケージの製造方法。
- 積層され且つ互いに電気的に接続された主パッケージと追加部分とを備えた複合型積層チップパッケージであって、
前記主パッケージは、上面、下面および4つの側面を有する本体と、前記本体の少なくとも1つの側面に配置された複数のワイヤを含む配線とを備え、
前記本体は、積層された複数の階層部分を含むと共に上面と下面を有する主要部分と、前記主要部分の上面と下面のうちの少なくとも上面に配置されて前記複数のワイヤに電気的に接続された複数の端子とを有し、
前記複数の階層部分の各々は、半導体チップと、前記複数のワイヤに電気的に接続された複数の電極とを含み、
前記複数の端子は、前記主要部分の上面に配置されて前記複数のワイヤに電気的に接続された複数の第1の端子を含み、
前記複数の第1の端子は、最も上に位置する階層部分における前記複数の電極を用いて構成され、
前記複数の電極は、前記半導体チップとの電気的接続のための複数の第1の電極と、前記半導体チップに接触しない複数の第2の電極とを含み、
前記複数のワイヤは、前記主要部分内の全ての階層部分に共通する用途を有する複数の共通ワイヤと、互いに異なる階層部分によって利用される複数の階層依存ワイヤとを含み、
前記複数の第1の電極は、前記複数の共通ワイヤに電気的に接続され、
前記複数の第2の電極は、前記複数の階層依存ワイヤに電気的に接続され、
前記複数の階層部分の各々は、更に、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続された選択的接続電極を含み、
前記複数の階層部分は、少なくとも1つの第1の種類の階層部分と、少なくとも1つの第2の種類の階層部分とを含み、
前記第1の種類の階層部分における前記半導体チップは正常に動作するものであり、前記第1の種類の階層部分では、前記複数の第1の電極は、前記半導体チップに接触してこれに電気的に接続され、
前記第2の種類の階層部分における前記半導体チップは正常に動作しないものであり、前記第2の種類の階層部分では、前記複数の第1の電極は、前記半導体チップに接触しておらず、
前記第1の種類の階層部分では、前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記階層依存ワイヤに電気的に接続され、
前記第2の種類の階層部分では、前記選択的接続電極が前記半導体チップに電気的に接続されていないことによって、前記半導体チップが前記階層依存ワイヤに電気的に接続されておらず、
前記追加部分は、
少なくとも1つの追加半導体チップと、
前記少なくとも1つの追加半導体チップが前記少なくとも1つの第2の種類の階層部分における半導体チップの代替となるように、前記主パッケージにおける前記複数の端子と前記少なくとも1つの追加半導体チップとの電気的接続関係を規定する追加部分配線とを備えたことを特徴とする複合型積層チップパッケージ。 - 前記複数の端子は、更に、前記主要部分の下面に配置されて前記複数のワイヤに電気的に接続された複数の第2の端子を含むことを特徴とする請求項12記載の複合型積層チップパッケージ。
- 前記追加部分は、上面、下面および4つの側面を有する追加部分本体を備え、
前記追加部分本体は、前記少なくとも1つの追加半導体チップを含み、
前記追加部分配線は、前記追加部分本体の少なくとも1つの側面に配置された複数の追加部分ワイヤと、前記追加部分本体の上面に配置されて前記複数の追加部分ワイヤに電気的に接続された複数の第1の追加部分端子と、前記追加部分本体の下面に配置されて前記複数の追加部分ワイヤに電気的に接続された複数の第2の追加部分端子とを含むことを特徴とする請求項12記載の複合型積層チップパッケージ。 - 前記階層部分内の半導体チップおよび前記追加半導体チップは、それぞれ、複数のメモリセルを含むことを特徴とする請求項12記載の複合型積層チップパッケージ。
- 前記階層部分内の半導体チップは、4つの側面を有し、
前記階層部分は、更に、前記半導体チップの4つの側面のうちの少なくとも1つの側面を覆う絶縁部を含み、
前記絶縁部は、前記複数のワイヤが配置された前記本体の前記少なくとも1つの側面に配置された少なくとも1つの端面を有することを特徴とする請求項12記載の複合型積層チップパッケージ。 - 請求項12記載の複合型積層チップパッケージを製造する方法であって、
前記主パッケージを作製する工程と、
前記追加部分を作製する工程と、
前記主パッケージと追加部分とを積層し且つ互いに電気的に接続する工程と
を備えたことを特徴とする複合型積層チップパッケージの製造方法。
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US8203216B2 (en) * | 2010-07-13 | 2012-06-19 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
US8253257B2 (en) * | 2011-01-26 | 2012-08-28 | Headway Technologies, Inc. | Layered chip package and method of manufacturing the same |
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US8344494B2 (en) * | 2011-04-11 | 2013-01-01 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
US8426981B2 (en) * | 2011-09-22 | 2013-04-23 | Headway Technologies, Inc. | Composite layered chip package |
US8710641B2 (en) * | 2012-03-16 | 2014-04-29 | Headway Technologies, Inc. | Combination for composite layered chip package |
US8912042B2 (en) | 2012-09-17 | 2014-12-16 | Headway Technologies, Inc. | Manufacturing method for layered chip packages |
CN107706170A (zh) | 2016-08-09 | 2018-02-16 | 晟碟信息科技(上海)有限公司 | 垂直半导体装置 |
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US10483239B2 (en) | 2016-12-20 | 2019-11-19 | Sandisk Semiconductor (Shanghai) Co. Ltd. | Semiconductor device including dual pad wire bond interconnection |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5648684A (en) | 1995-07-26 | 1997-07-15 | International Business Machines Corporation | Endcap chip with conductive, monolithic L-connect for multichip stack |
US5953588A (en) | 1996-12-21 | 1999-09-14 | Irvine Sensors Corporation | Stackable layers containing encapsulated IC chips |
JP4361670B2 (ja) * | 2000-08-02 | 2009-11-11 | 富士通マイクロエレクトロニクス株式会社 | 半導体素子積層体、半導体素子積層体の製造方法、及び半導体装置 |
US20020096760A1 (en) | 2001-01-24 | 2002-07-25 | Gregory Simelgor | Side access layer for semiconductor chip or stack thereof |
US6734370B2 (en) | 2001-09-07 | 2004-05-11 | Irvine Sensors Corporation | Multilayer modules with flexible substrates |
US6855572B2 (en) | 2002-08-28 | 2005-02-15 | Micron Technology, Inc. | Castellation wafer level packaging of integrated circuit chips |
JP2004281633A (ja) * | 2003-03-14 | 2004-10-07 | Olympus Corp | 積層モジュール |
US7609561B2 (en) | 2006-01-18 | 2009-10-27 | Apple Inc. | Disabling faulty flash memory dies |
KR100833589B1 (ko) | 2006-03-29 | 2008-05-30 | 주식회사 하이닉스반도체 | 스택 패키지 |
KR100832845B1 (ko) | 2006-10-03 | 2008-05-28 | 삼성전자주식회사 | 반도체 패키지 구조체 및 그 제조 방법 |
JP5049684B2 (ja) | 2007-07-20 | 2012-10-17 | 新光電気工業株式会社 | 積層型半導体装置及びその製造方法 |
US7911045B2 (en) | 2007-08-17 | 2011-03-22 | Kabushiki Kaisha Toshiba | Semiconductor element and semiconductor device |
KR20090034081A (ko) | 2007-10-02 | 2009-04-07 | 삼성전자주식회사 | 적층형 반도체 패키지 장치 및 이의 제작 방법 |
US7745259B2 (en) * | 2008-06-30 | 2010-06-29 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
US7964976B2 (en) * | 2008-08-20 | 2011-06-21 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
US7557439B1 (en) * | 2008-09-29 | 2009-07-07 | Tdk Corporation | Layered chip package that implements memory device |
JP2010140981A (ja) | 2008-12-10 | 2010-06-24 | Elpida Memory Inc | チップ構造、チップ積層構造、半導体パッケージ構造、およびメモリ。 |
US7968374B2 (en) * | 2009-02-06 | 2011-06-28 | Headway Technologies, Inc. | Layered chip package with wiring on the side surfaces |
US8274165B2 (en) | 2009-02-10 | 2012-09-25 | Headway Technologies, Inc. | Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same |
JP5280880B2 (ja) | 2009-02-10 | 2013-09-04 | 株式会社日立製作所 | 半導体集積回路装置 |
US7902677B1 (en) * | 2009-10-28 | 2011-03-08 | Headway Technologies, Inc. | Composite layered chip package and method of manufacturing same |
US8203216B2 (en) * | 2010-07-13 | 2012-06-19 | Headway Technologies, Inc. | Layered chip package and method of manufacturing same |
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