JP2012015279A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 185
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 abstract description 47
- 239000010408 film Substances 0.000 description 69
- 239000010410 layer Substances 0.000 description 56
- 238000009792 diffusion process Methods 0.000 description 44
- 230000015556 catabolic process Effects 0.000 description 13
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000008646 thermal stress Effects 0.000 description 5
- 239000013039 cover film Substances 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000008642 heat stress Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Abstract
【解決手段】本発明にかかる半導体装置は、多角形の外形を有する半導体基板30を有する。半導体基板30上には、アクティブ領域21が形成される。アクティブ領域21及び半導体基板30上には、層間絶縁膜7が形成される。また、コーナー部22に沿ったEQR電極の曲線部8bを有する、EQR電極8が形成されている。EQR電極8は、層間絶縁膜7中にアクティブ領域21を囲んで埋設されている。さらに、EQR電極の曲線部8bとEQR電極の曲線部8bの外側の半導体基板30とに接し、少なくとも側壁が層間絶縁膜7に覆われたEQRコンタクト10aが形成されている。
【選択図】図1
Description
以下、図面を参照して本発明の実施の形態について説明する。まず、実施の形態1にかかる半導体装置について説明する。図1は、実施の形態1にかかる半導体装置100の構造を示す平面図である。半導体装置100は、四角形状の外形を有しており、中央部にアクティブ領域21が配置される。アクティブ領域21は、例えばMOSFETやIGBT(Insulated Gate Bipolar Transistor)などのセルが配置される。アクティブ領域21は、それぞれのセルと接続されたソース電極(図示せず)に覆われる。
次に、実施の形態2にかかる半導体装置について説明する。図4は、実施の形態2にかかる半導体装置200の構造を示す平面図である。図5は、実施の形態2にかかる半導体装置200のコーナー部23を拡大表示した平面図である。図4及び5に示すように、半導体装置200は、半導体装置100のEQRコンタクト10aを、EQRコンタクト10bに置き換えたものである。半導体装置200のその他の構成は、半導体装置100と同様であるので、説明を省略する。また、半導体装置200の断面構造は、図3に示す半導体装置100の断面構造と同様であるので、説明を省略する。
次に、実施の形態3にかかる半導体装置について説明する。図6は、実施の形態3にかかる半導体装置300の構造を示す平面図である。図7は、実施の形態3にかかる半導体装置300のコーナー部24を拡大表示した平面図である。図6及び7に示すように、半導体装置300は、半導体装置100のEQRコンタクト10aを、EQRコンタクト10cに置き換えたものである。半導体装置300のその他の構成は、半導体装置100と同様であるので、説明を省略する。なお、図6及び7では、EQR電極8は層間絶縁膜7で覆われているが、EQR電極8の位置を説明するため、層間絶縁膜7を省略している。
次に、実施の形態4にかかる半導体装置について説明する。図11は、実施の形態4にかかる半導体装置400の構造を示す平面図である。図12は、実施の形態4にかかる半導体装置400のコーナー部25を拡大表示した平面図である。図11及び12に示すように、半導体装置400は、半導体装置100のEQRコンタクト10aを、EQRコンタクト10dに置き換えたものである。半導体装置400のその他の構成は、半導体装置100と同様であるので、説明を省略する。また、半導体装置400の断面構造は、図3に示す半導体装置100の断面構造と同様であるので、説明を省略する。
なお、本発明は上記実施の形態に限られたものではなく、趣旨を逸脱しない範囲で適宜変更することが可能である。例えば、EQRコンタクト10a〜dは、タングステンに限られない。EQRコンタクト10a〜dは、導電性を有する他の材料を用いることが可能である。よって、EQRコンタクト10a〜dには、例えばアルミニウムを用いることが可能である。
2 エピタキシャル層
3 ベース拡散領域
4 チャネルストッパ層
4a ソース拡散領域
5 ドレイン電極
6 第2のゲート電極
6a 第2のゲート電極の直線部
6b 第2のゲート電極の曲線部
7 層間絶縁膜
8 EQR電極
8a EQR電極の直線部
8b EQR電極の曲線部
9 第1のゲート電極
10a〜d EQRコンタクト
12 高濃度拡散領域
13 ソース電極
14 ゲート酸化膜
15 トレンチソースコンタクト
16 端面
17 レジストマスク
18 タングステン
21 アクティブ領域
22〜25 コーナー部
30 半導体基板
51 アクティブ領域
52 チャネルストッパ領域
61 半導体基板
62 エピタキシャル層
63 ベース拡散領域
64 ソース拡散領域
65 ゲート酸化膜
66 第1のゲート電極
67 層間絶縁膜
68 ソース電極
69 ドレイン電極
71 チャネルストッパ層
72 第1のEQR電極
73 第2のEQR電極
74 フィールド酸化膜
75 端面
76 第2のゲート電極
100、200、300、400、500 半導体装置
Claims (15)
- 多角形の外形を有する半導体基板と、
前記半導体基板上に形成されたアクティブ領域と、
前記アクティブ領域及び前記半導体基板上に形成された絶縁膜と、
前記絶縁膜中に前記アクティブ領域を囲んで埋設され、前記多角形のコーナー部に沿って形成された曲線部を有するEQR電極と、
前記EQR電極の前記曲線部と、前記EQR電極の前記曲線部の外側の半導体基板と、に接して形成され、少なくとも側壁が前記絶縁膜に覆われたコンタクトと、を備える、
半導体装置。 - 前記コンタクトは、前記絶縁膜に埋設されることを特徴とする、
請求項1に記載の半導体装置。 - 前記コンタクトは、前記曲線部のそれぞれに複数形成されることを特徴とする、
請求項1又は2に記載の半導体装置。 - 前記コンタクトは、長辺が前記曲線部の外周の法線方向に沿った四角形状を有することを特徴とする、
請求項1乃至3のいずれか一項に記載の半導体装置。 - 前記コンタクトは、短片の長さが1μm以下であることを特徴とする、
請求項4に記載の半導体装置。 - 前記コンタクトは、短片の長さが0.8μm以下であることを特徴とする、
請求項4又は5に記載の半導体装置。 - 前記多角形は、四角形であることを特徴とする、
請求項1乃至6のいずれか一項に記載の半導体装置。 - 前記コンタクトは、アルミニウム又はタングステンにより形成されることを特徴とする、
請求項1乃至7のいずれか一項に記載の半導体装置。 - 前記半導体基板は、
第1導電型の第1の半導体層と、
前記第1の半導体層上に前記第1導電型の第2の半導体層と、を備え、
前記コンタクトは、前記第2の半導体層を介して前記半導体基板の端面と電気的に接続されることを特徴とする、
請求項1乃至8のいずれか一項に記載の半導体装置。 - 前記半導体基板は、
前記第2の半導体層の一部に形成された第2導電型の第3の半導体層をさらに備え、
前記コンタクトは、前記第3の半導体層を介して前記半導体基板の端面と電気的に接続されることを特徴とする、
請求項9に記載の半導体装置。 - 前記半導体基板は、
前記第3の半導体層上に形成された前記第1導電型の第4の半導体層をさらに備え、
前記コンタクトは、さらに前記第4の半導体層を介して前記半導体基板の端面と電気的に接続されることを特徴とする、
請求項10に記載の半導体装置。 - 前記第3の半導体層は、前記コンタクトの底面と接し、
前記第4の半導体層は、前記コンタクトの側面と接することを特徴とする、
請求項11に記載の半導体装置。 - 前記第4の半導体層は、前記第1の半導体層及び前記第2の半導体層よりも高い不純物濃度を有することを特徴とする、
請求項11又は12に記載の半導体装置。 - 前記半導体基板は、
前記第3の半導体層と前記コンタクトとの間に形成され、前記第3の半導体層よりも高い不純物濃度を有する前記第2導電型の第5の半導体層を備えることを特徴とする、
請求項13に記載の半導体装置。 - 多角形の外形を有する半導体基板上のアクティブ領域を覆うとともに前記アクティブ領域を囲むEQR電極が埋設された絶縁膜を形成し、
前記絶縁膜の一部を除去することにより、前記アクティブ領域においてソース電極と電気的に接続される部分の半導体基板と、前記多角形のそれぞれのコーナー部において当該コーナー部に沿って形成された前記EQR電極の曲線部及び前記曲線部の外側の半導体基板と、を露出させ、
導電性材料を、前記絶縁膜と、前記絶縁膜が除去されたことにより露出した前記半導体基板及び前記EQR電極の前記曲線部と、の上に堆積させ、
前記導電性材料が前記アクティブ領域の前記絶縁膜の上面と同じ高さになるまでエッチングし、
前記アクティブ領域の少なくとも前記ソースコンタクト上に前記ソース電極を形成し、
前記コーナー部おいて前記絶縁膜が除去された部分のそれぞれは、前記前記アクティブ領域において前記絶縁膜が除去された部分のそれぞれよりも大きな開口を有する、
半導体装置の製造方法。
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