JP7208875B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7208875B2 JP7208875B2 JP2019162271A JP2019162271A JP7208875B2 JP 7208875 B2 JP7208875 B2 JP 7208875B2 JP 2019162271 A JP2019162271 A JP 2019162271A JP 2019162271 A JP2019162271 A JP 2019162271A JP 7208875 B2 JP7208875 B2 JP 7208875B2
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Description
(第1実施形態)
図1及び図2は、第1実施形態に係る半導体装置を表す平面図である。
(効果1)
半導体装置100rがオフ状態のとき、半導体装置100rの外周には電界が発生する。この電界により、半導体装置100rの外部や絶縁部42に存在する外部荷電の一部が、半導体SLに向けて引き寄せられる。例えば、引き寄せられた外部電荷が絶縁部42の半絶縁層41近傍に蓄積されると、外部電荷によって電界が形成される。外部電荷によって形成された電界が半導体層SLに届くと、半導体層SLの上面に電荷が蓄積される。蓄積された電荷は、空乏層の広がりに影響を及ぼす。この結果、半導体層SLにおける空乏層の広がりが変動し、耐圧が低下する。
(効果2)
半導体装置100では、n-形半導体領域1とp-形環状領域10a~10dのそれぞれとの間に接合容量が形成されている。半導体装置100rでは、n-形半導体領域1とp形環状領域11a~11dのそれぞれとの間に接合容量が形成されている。これらの接合容量は、半導体装置100及び100rがターンオフされたときに充電され、半導体装置100及び100rがターンオンされたときに放電される。半導体装置100及び100rをターンオフしたとき、接合容量が充電されるまでの間、p-形環状領域10a~10d及びp形環状領域11a~11dのそれぞれの電位が一時的に不安定となる。接合容量が充電されるまでの時間が長いと、耐圧が安定するまでに要する時間が長くなる。このため、接合容量の充電又は放電に要する時間は、短いことが望ましい。
(効果3)
半導体装置100がターンオフしたとき、p形半導体領域2から外周に向けて空乏層が広がる。このとき、n-形半導体領域1において空乏層が広がっていない領域の電位は、下部電極21の電位と等しい。一方で、EQPR電極23から上部電極22には、空乏層が広がり始めるとともに電流が流れる。すなわち、EQPR電極23から上部電極22に向けて、電圧降下が生じる。このため、上部電極22及び導電層30a~30cの電位は、それらの下に位置するn-形半導体領域1の領域1a~1dの電位よりもそれぞれ低くなる。この電位差により、領域1a~1dのそれぞれの上面に正孔が蓄積され、p形チャネルが形成される。p形チャネルにより、p-形環状領域10a~10d及びp形半導体領域2が互いに電気的に接続される。
(第1変形例)
図7は、第1実施形態の第1変形例に係る半導体装置の一部を表す断面図である。
(第2変形例)
図8は、第1実施形態の第2変形例に係る半導体装置の一部を表す断面図である。
(第2実施形態)
図9は、第2実施形態に係る半導体装置の一部を表す断面図である。
(第3実施形態)
図10は、第3実施形態に係る半導体装置の一部を表す断面図である。
Claims (12)
- 第1電極と、
前記第1電極の上に設けられ、前記第1電極と電気的に接続された第1導電形の第1半導体領域と、
前記第1半導体領域の上に設けられた第2導電形の第2半導体領域と、
前記第1半導体領域の上に設けられ、前記第2半導体領域を囲み、前記第1半導体領域よりも高い第1導電形の不純物濃度を有する第1導電形の第3半導体領域と、
前記第2半導体領域と前記第3半導体領域との間に設けられ、前記第2半導体領域及び前記第3半導体領域から離れ、前記第2半導体領域を囲む第2導電形の第1環状領域と、
前記第1環状領域と前記第3半導体領域との間に設けられ、前記第1環状領域及び前記第3半導体領域から離れ、前記第1環状領域を囲む第2導電形の第2環状領域と、
前記第2半導体領域の上に設けられ、前記第2半導体領域と電気的に接続された第2電極と、
前記第3半導体領域の上に設けられ、且つ前記第2環状領域の一部と、前記第2環状領域と前記第3半導体領域との間に位置する前記第1半導体領域の一部と、の上に絶縁層を介して設けられ、前記第2電極を囲み、前記第3半導体領域と電気的に接続された第3電極と、
前記第1環状領域と、前記第2環状領域の別の一部と、前記第1環状領域と前記第2環状領域との間に位置する前記第1半導体領域の一部と、の上に前記絶縁層を介して設けられ、前記第2電極及び前記第3電極から離れ、前記第2電極を囲む第1導電層と、
前記第2電極、前記第1導電層、及び前記第3電極に接する半絶縁層と、
を備えた半導体装置。 - 前記第1環状領域と前記第2半導体領域との間に設けられ、前記第1環状領域及び前記第2半導体領域から離れ、前記第2半導体領域を囲む第2導電形の第3環状領域と、
前記第1環状領域と、前記第3環状領域と、前記第1環状領域と前記第3環状領域との間に位置する前記第1半導体領域の一部と、の上に前記絶縁層を介して設けられ、前記第1導電層及び前記第2電極から離れ、前記第2電極を囲む第2導電層と、
をさらに備えた請求項1記載の半導体装置。 - 第1電極と、
前記第1電極の上に設けられ、前記第1電極と電気的に接続された第1導電形の第1半導体領域と、
前記第1半導体領域の上に設けられた第2導電形の第2半導体領域と、
前記第1半導体領域の上に設けられ、前記第2半導体領域を囲み、前記第1半導体領域よりも高い第1導電形の不純物濃度を有する第1導電形の第3半導体領域と、
前記第2半導体領域と前記第3半導体領域との間に設けられ、前記第2半導体領域及び前記第3半導体領域から離れ、前記第2半導体領域を囲む第2導電形の第1環状領域と、
前記第2半導体領域の上に設けられ、前記第2半導体領域と電気的に接続された第2電極と、
前記第3半導体領域の一部の上に設けられ、前記第2電極を囲み、前記第3半導体領域と電気的に接続された第3電極と、
前記第1環状領域と、前記第3半導体領域の別の一部と、前記第1環状領域と前記第3半導体領域との間に位置する前記第1半導体領域の一部と、の上に絶縁層を介して設けられ、前記第2電極及び前記第3電極から離れ、前記第2電極を囲む第1導電層と、
前記第2電極、前記第1導電層、及び前記第3電極に接する半絶縁層と、
を備えた半導体装置。 - 前記第1環状領域と前記第2半導体領域との間に設けられ、前記第1環状領域及び前記第2半導体領域から離れ、前記第2半導体領域を囲む第2導電形の第2環状領域と、
前記第1環状領域と、前記第2環状領域と、前記第1環状領域と前記第2環状領域との間に位置する前記第1半導体領域の一部と、の上に前記絶縁層を介して設けられ、前記第1導電層及び前記第2電極から離れ、前記第2電極を囲む第2導電層と、
をさらに備えた請求項3記載の半導体装置。 - 前記第1環状領域における第2導電形の不純物濃度は、前記第2半導体領域における第2導電形の不純物濃度よりも低い、請求項1~4のいずれか1つに記載の半導体装置。
- 第1電極と、
前記第1電極の上に設けられ、前記第1電極と電気的に接続された第1導電形の第1半導体領域と、
前記第1半導体領域の上に設けられた第2導電形の第2半導体領域と、
前記第1半導体領域の上に設けられ、前記第2半導体領域を囲み、前記第1半導体領域よりも高い第1導電形の不純物濃度を有する第1導電形の第3半導体領域と、
前記第2半導体領域と前記第3半導体領域との間において互いに離れて設けられ、前記第2半導体領域及び前記第3半導体領域から離れ、それぞれが前記第2半導体領域を囲む第2導電形の複数の環状領域と、
前記第2半導体領域の上に設けられ、前記第2半導体領域と電気的に接続された第2電極と、
前記第3半導体領域の上に設けられ、前記第2電極を囲み、前記第3半導体領域と電気的に接続された第3電極と、
前記複数の環状領域の上に絶縁層を介して設けられ、前記第2電極と前記第3電極との間において互いに離れ、前記第2電極及び前記第3電極から離れ、それぞれが前記第2電極を囲む複数の導電層と、
前記第2電極、前記複数の導電層、及び前記第3電極に接する半絶縁層と、
を備え、
前記複数の導電層のそれぞれは、互いに隣り合う2つの前記環状領域と、前記2つの環状領域の間に位置する前記第1半導体領域の一部と、の上に設けられ、
前記第3電極の一部は、前記複数の環状領域のうち最外周に位置する前記環状領域と、前記最外周に位置する環状領域と前記第3半導体領域との間に位置する前記第1半導体領域の一部と、の上に前記絶縁層を介して設けられた半導体装置。 - 第1電極と、
前記第1電極の上に設けられ、前記第1電極と電気的に接続された第1導電形の第1半導体領域と、
前記第1半導体領域の上に設けられた第2導電形の第2半導体領域と、
前記第1半導体領域の上に設けられ、前記第2半導体領域を囲み、前記第1半導体領域よりも高い第1導電形の不純物濃度を有する第1導電形の第3半導体領域と、
前記第2半導体領域と前記第3半導体領域との間において互いに離れて設けられ、前記第2半導体領域及び前記第3半導体領域から離れ、それぞれが前記第2半導体領域を囲む第2導電形の複数の環状領域と、
前記第2半導体領域の上に設けられ、前記第2半導体領域と電気的に接続された第2電極と、
前記第3半導体領域の一部の上に設けられ、前記第2電極を囲み、前記第3半導体領域と電気的に接続された第3電極と、
前記複数の環状領域の上に絶縁層を介して設けられ、前記第2電極と前記第3電極との間において互いに離れ、前記第2電極及び前記第3電極から離れ、それぞれが前記第2電極を囲む複数の導電層と、
前記第2電極、前記複数の導電層、及び前記第3電極に接する半絶縁層と、
を備え、
前記複数の導電層のそれぞれは、互いに隣り合う2つの前記環状領域と、前記2つの環状領域の間に位置する前記第1半導体領域の一部と、の上に設けられ、
前記複数の導電層のうち最外周に位置する前記導電層は、前記複数の環状領域のうち最外周に位置する前記環状領域と、前記第3半導体領域の別の一部と、前記最外周に位置する環状領域と前記第3半導体領域との間に位置する前記第1半導体領域の一部と、の上に前記絶縁層を介して設けられた半導体装置。 - 前記複数の環状領域のそれぞれにおける第2導電形の不純物濃度は、前記第2半導体領域における第2導電形の不純物濃度よりも低い、請求項6又は7に記載の半導体装置。
- 前記第1環状領域の第2導電形の不純物総量は、0.5×1013atom/cm2以上、3.0×1013atom/cm2以下である請求項1~5のいずれか1つに記載の半導体装置。
- 前記半絶縁層の抵抗率は、1.0×108[Ω・cm]以上1.0×1013[Ω・cm]未満である請求項1~9のいずれか1つに記載の半導体装置。
- 前記第2半導体領域の上に設けられた第1導電形の第4半導体領域と、
ゲート絶縁層を介して前記第2半導体領域と対向するゲート電極と、
をさらに備えた請求項1~10のいずれか1つに記載の半導体装置。 - 前記第1電極と前記第1半導体領域との間に設けられた第2導電形の第5半導体領域をさらに備えた請求項11記載の半導体装置。
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