JP2011129934A - 可変抵抗メモリ装置及びその製造方法 - Google Patents
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- G—PHYSICS
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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Abstract
【解決手段】可変抵抗メモリ装置及びその製造方法を提供する。基板上に複数の下部電極を構成し、前記下部電極を露出し、第1方向に延長されるトレンチを含む第1層間絶縁膜を構成し、前記第1層間絶縁膜上に前記第1方向と交差する第2方向に延長される上部電極を構成し、前記トレンチ内に前記上部電極の側壁にアライメントされる側壁を有する可変抵抗パターンを形成する。
【選択図】図2
Description
また、本発明が解決しようとする他の課題等は、次の説明から明らかになるであろう。
110 第1層間絶縁膜
112 下部電極
115 トレンチ
120 第2層間絶縁膜
122 可変抵抗ライン
123 可変抵抗パターン
128 熱損失防止パターン
131 絶縁パターン
135 拡散防止パターン
137 上部電極
138 側壁
140 第3層間絶縁膜
141 コンタクトプラグ
145 第4層間絶縁膜
1000 メモリシステム
1100 可変抵抗メモリ装置
1200 メモリコントローラ
1300 半導体メモリ装置
1450 システムバス
1500 中央処理装置
1600 ユーザインターフェース
1700 電源供給装置
Claims (10)
- 基板と、
前記基板上の複数の下部電極と
複数の前記下部電極を露出し、第1方向に延長されるトレンチを含む第1層間絶縁膜と、
前記第1層間絶縁膜上に形成され、前記第1方向と交差する第2方向に延長される上部電極と、
前記トレンチ内に形成され、前記上部電極の側壁にアライメントされる側壁を含む複数の可変抵抗パターンを有することを特徴とする可変抵抗メモリ装置。 - 前記可変抵抗パターンのアライメントされた前記側壁は前記第2方向と平行であることを特徴とする請求項1に記載の可変抵抗メモリ装置。
- 前記トレンチは前記第2方向に隣接する2つの下部電極をともに露出することを特徴とする請求項1に記載の可変抵抗メモリ装置。
- 基板と、
前記基板上の複数の下部電極と、
前記下部電極上に形成され、第1方向に延長される複数の可変抵抗ラインと、
前記可変抵抗ライン上に形成され、前記第1方向と交差する第2方向に延長される上部電極を含むことを特徴とする可変抵抗メモリ装置。 - 基板上に複数の下部電極を形成し、
前記下部電極上に第1方向に延長される複数の可変抵抗ラインを形成し、
前記可変抵抗ライン上に、前記第1方向と交差する第2方向に延長される上部電極を形成することを特徴とする可変抵抗メモリ装置の製造方法。 - 前記上部電極を形成することは、
前記可変抵抗ライン上に導電膜を形成し、
前記導電膜上に前記第2方向に延長されるマスクパターンを形成し、
前記マスクパターンによって前記導電膜を前記第2方向に延長されるようにパターニングすることを特徴とする請求項5に記載の可変抵抗メモリ装置の製造方法。 - 前記マスクパターンによってパターニングすることは、前記可変抵抗ラインをパターニングして前記第1方向に分離された可変抵抗パターンを形成することを特徴とする請求項6に記載の可変抵抗メモリ装置の製造方法。
- 前記下部電極は前記第2方向への長さが前記第1方向への長さよりさらに長い上面を有するよう形成されることを特徴とする請求項5に記載の可変抵抗メモリ装置の製造方法。
- 前記可変抵抗ラインを形成することは、
前記下部電極上に層間絶縁膜を形成し、
前記層間絶縁膜に前記第1方向に延長され、前記下部電極の上面の少なくとも一部を露出するトレンチを形成し、
前記トレンチ上に可変抵抗物質膜を形成することを特徴とする請求項5に記載の可変抵抗メモリ装置の製造方法。 - 前記トレンチは前記第2方向に隣接する2つの下部電極をともに露出するよう形成されることを特徴とする請求項9に記載の可変抵抗メモリ装置の製造方法。
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KR1020090128097A KR101617381B1 (ko) | 2009-12-21 | 2009-12-21 | 가변 저항 메모리 장치 및 그 형성 방법 |
KR10-2009-0128097 | 2009-12-21 |
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US (2) | US8552412B2 (ja) |
JP (1) | JP5660882B2 (ja) |
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CN (1) | CN102104055B (ja) |
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KR20110076394A (ko) * | 2009-12-29 | 2011-07-06 | 삼성전자주식회사 | 상변화 메모리 장치 |
KR20120104031A (ko) * | 2011-03-11 | 2012-09-20 | 삼성전자주식회사 | 상변화 물질층, 상변화 물질층의 형성 방법, 상변화 메모리 장치 및 상변화 메모리 장치의 제조 방법 |
KR101872949B1 (ko) * | 2011-05-17 | 2018-07-02 | 삼성전자주식회사 | 상변화 메모리 장치 및 이의 제조 방법 |
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