JP4551321B2 - 電子部品実装構造及びその製造方法 - Google Patents
電子部品実装構造及びその製造方法 Download PDFInfo
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Description
図1は、本発明の第1の実施形態の電子部品実装構造を示す断面図である。
図8は本発明の第2の実施形態の電子部品実装構造の製造方法を示す断面図、図9は同じくその模式平面図(全体図)である。なお、図8において、図5(b)と同一物には同一符号を付している。
図10(a),(b)は、本発明の第3の実施形態の電子部品実装構造の製造方法を示す断面図である。
図11は、本発明の第4の実施形態の電子部品実装構造を示す断面図である。
10,60…ユニット、
11,61…絶縁層、
21,71…基板、
21a…枠状の金属膜、
22,72…ソルダーレジスト層、
23…はんだ層、
24…端子、
25,75…ドライフィルム、
26,76…配線、
27,77…半導体チップ、
28,78…バンプ、
29,79…アンダーフィル(保護膜)、
30,80…絶縁性樹脂層、
31…コンタクトビア、
81…貫通電極、
83…エッチングレジスト膜。
Claims (9)
- 複数のシート状のユニットが厚さ方向に積層されて構成された電子部品実装構造において、前記ユニットが、第1の絶縁層と、
前記第1の絶縁層の一方の面上に形成された配線と、
前記配線に接続された電子部品と、
前記第1の絶縁層の前記一方の面側に形成されて前記電子部品を覆う第2の絶縁層と、
前記配線と他のユニットの配線とを電気的に接続する接続部とを有し、
厚さ方向に隣り合うユニットにおいて、前記第1の絶縁層、前記電子部品、前記配線及び前記第2の絶縁層の配置が対称であり、かつ、
前記接続部が、前記第1の絶縁層を貫通して形成されて前記配線の一方の面に接合された端子と、前記第2の絶縁層を貫通して形成されて前記配線の他方の面に接合されたコンタクトビアとにより構成され、
前記端子が前記第1の絶縁層の表面から突出しており、
前記コンタクトビアの頂部が前記第2の絶縁層の表面から突出しており、
前記各ユニットは前記端子同士又は前記コンタクトビア同士により接続されていることを特徴とする電子部品実装構造。 - 前記第1の絶縁層が、ソルダーレジストからなることを特徴とする請求項1に記載の電子部品実装構造。
- 前記各ユニットの前記端子同士又は前記コンタクトビア同士は、異方性導電フィルムを介して接続されていることを特徴とする請求項1に記載の電子部品実装構造。
- 前記電子部品が半導体チップであることを特徴とする請求項1に記載の電子部品実装構造。
- 前記半導体チップが前記配線とフリップチップ接合していることを特徴とする請求項4に記載の電子部品実装構造。
- 基板上に絶縁性樹脂からなる第1の絶縁層を形成する第1工程と、
前記第1の絶縁層をパターニングして開口部を形成する第2工程と、
前記開口部の内側に露出した前記基板をエッチングして窪みを形成する第3工程と、
前記開口部の内側に金属を充填して端子を形成する第4工程と、
前記第1の絶縁層の上に、前記端子と接続する配線を形成する第5工程と、
前記配線の上に電子部品を接合する第6工程と、
前記第1の絶縁層の上に前記電子部品を覆う第2の絶縁層を形成する第7工程と、
前記第2の絶縁層の上面から前記配線に到達する孔を形成する第8工程と、
前記孔内に金属を充填してコンタクトビアを形成する第9工程と、
前記基板を除去する第10工程とを遂行することにより、
前記第1の絶縁層と、前記第1の絶縁層の一方の面上に形成された前記配線と、前記配線に接続された前記電子部品と、前記第1の絶縁層の一方の面側に形成されて前記電子部品を覆う前記第2の絶縁層と、前記配線と電気的に接続した前記端子及び前記コンタクトビアからなる接続部とにより構成されるシート状のユニットを複数用意し、
それらのユニットを、厚さ方向に隣り合うユニットの向きを交互に逆に配置して相互に積層して前記端子同士又は前記コンタクト同士を接合し、前記接続部を介して各ユニットの電子部品を相互に電気的に接続することを特徴とする電子部品実装構造の製造方法。 - 前記第9工程の後に、2つのユニットを前記電子部品が搭載された面を向かい合わせて接合し、その後、前記第10工程を実施して前記基板を剥離することを特徴とする請求項6に記載の電子部品実装構造の製造方法。
- 前記第10工程において、前記基板のうち縁部の部分を枠状に残し、その後各ユニットを接合した後に前記枠状の部分を切断除去することを特徴とする請求項6に記載の電子部品実装構造の製造方法。
- 前記第1工程において、前記基板の下面に第3の絶縁層を形成し、
前記第9工程の終了から第10工程の開始までの間に、前記第3の絶縁層を除去することを特徴とする請求項6に記載の電子部品実装構造の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005373859A JP4551321B2 (ja) | 2005-07-21 | 2005-12-27 | 電子部品実装構造及びその製造方法 |
US11/486,051 US7843059B2 (en) | 2005-07-21 | 2006-07-14 | Electronic parts packaging structure |
US12/926,072 US8402644B2 (en) | 2005-07-21 | 2010-10-25 | Method of manufacturing an electronic parts packaging structure |
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US20110039370A1 (en) | 2011-02-17 |
US7843059B2 (en) | 2010-11-30 |
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US8402644B2 (en) | 2013-03-26 |
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