JP2009267211A - 半導体装置およびその製造方法 - Google Patents
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- 229910052796 boron Inorganic materials 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
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Abstract
【解決手段】半導体装置は、n型の第1のウェル拡散層12と、n型の第2のウェル拡散層15と、p型のソース拡散層13と、p型の第3のウェル拡散層19と、p型のドレイン拡散層14と、ゲート絶縁膜16およびゲート電極17と、素子分離用絶縁膜18と、バッファ層21とを備えている。バッファ層21は、第3のウェル拡散層19のうちソース拡散層13に対向する側の端部に接し、第1のウェル拡散層12と第3のウェル拡散層19との間であってゲート絶縁膜16の直下から第3のウェル拡散層19の不純物濃度分布の曲率ピーク位置よりも深い位置に至る領域に形成され、第3のウェル拡散層19よりも不純物濃度が低い。
【選択図】図1
Description
以下、本発明の第1の実施形態に係る半導体装置について、図面を参照しながら説明する。図1は、本発明の第1の実施形態に係る半導体装置である高耐圧Pチャネル型MOSトランジスタの主要部分を示す断面図である。
以下、本発明の第2の実施形態に係る半導体装置について、図面を参照しながら説明する。
以下、本発明の第3の実施形態に係る半導体装置について、図面を参照しながら説明する。
以下、本発明の第4の実施形態に係る半導体装置について、図面を参照しながら説明する。
さらに、第2の実施形態の半導体装置と同様に、高濃度N型埋め込み拡散層41がN−型ウェル拡散層12および低濃度P−型拡散層19の下に、これらの層に接するように設けられているので、電界集中箇所を高濃度N型埋め込み拡散層41の下部に移動させることができる。このため、耐圧が大幅に向上するとともに、低閾値電圧を実現することができる。
12 N−型ウェル拡散層
13 ソースP+型拡散層
14 ドレインP+拡散層
15 N−型ウェル拡散層
16 ゲート酸化膜
17 ゲート電極
18 LOCOS酸化膜
19 低濃度P−型拡散層
20 P型表面拡散層
21 低濃度P−型バッファ拡散層
41 高濃度N型埋め込み拡散層
42、62 PN接合面
63 低濃度P−型バッファ拡散層
83 P型基板領域
91、93、95 リン
92、94、97、98 注入マスク
96、99 ボロン
Claims (10)
- 半導体基板と、
前記半導体基板の上部に形成された第1導電型の第1のウェル拡散層と、
前記第1のウェル拡散層の上部に形成された第1導電型の第2のウェル拡散層と、
前記第2のウェル拡散層の上部に形成された第2導電型のソース拡散層と、
前記半導体基板の上部であって前記第2のウェル拡散層と離れた位置に形成された第2導電型の第3のウェル拡散層と、
前記第3のウェル拡散層の上部に形成された第2導電型のドレイン拡散層と、
前記第2のウェル拡散層、前記第1のウェル拡散層、および前記第3のウェル拡散層の上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成された前記ゲート電極と、
前記第3のウェル拡散層の上であって、前記ゲート絶縁膜に連設されるとともに、前記ゲート絶縁膜と前記ドレイン拡散層との間に形成された素子分離用絶縁膜と、
前記第3のウェル拡散層のうち前記ソース拡散層に対向する側の端部に接し、前記第1のウェル拡散層と前記第3のウェル拡散層との間であってゲート絶縁膜の直下から前記第3のウェル拡散層の不純物濃度分布の曲率ピーク位置よりも深い位置に至る領域に形成され、前記第3のウェル拡散層よりも不純物濃度が低い第2導電型のバッファ層とを備えている半導体装置。 - 前記第2のウェル拡散層、前記第1のウェル拡散層、前記バッファ層および前記第3のウェル拡散層の表面部であって前記ゲート絶縁膜の直下に形成された第2導電型の表面拡散層をさらに備えていることを特徴とする請求項1に記載の半導体装置。
- 前記第3のウェル拡散層は前記第1のウェル拡散層の上部に形成されており、
前記バッファ層は前記第1のウェル拡散層の上部のうち第3のウェル拡散層が形成されていない部分と前記第3のウェル拡散層との間に形成されていることを特徴とする請求項1または2に記載の半導体装置。 - 前記半導体基板のうち、前記第1のウェル拡散層、前記バッファ層、および前記第3のウェル拡散層の底部に接する領域に形成された第1導電型の埋め込み拡散層をさらに備えていることを特徴とする請求項1または2に記載の半導体装置。
- 前記第1のウェル拡散層は、前記第3のウェル拡散層よりも前記ソース拡散層に近い位置に形成されていることを特徴とする請求項1、2、4のうちいずれか1つに記載の半導体装置。
- 前記バッファ層は、前記半導体基板と同一材料で構成され、且つ前記半導体基板と同じ濃度の第2導電型の不純物を含んでいることを特徴とする請求項4に記載の半導体装置。
- 前記バッファ層は、前記半導体基板よりも高濃度の第2導電型の不純物を含んでいることを特徴とする請求項1〜6のうちいずれか1つに記載の半導体装置。
- 半導体基板と、
前記半導体基板の上部に形成された第1導電型の第1のウェル拡散層と、
前記第1のウェル拡散層の上部に形成された第1導電型の第2のウェル拡散層と、
前記第2のウェル拡散層の上部に形成された第2導電型のソース拡散層と、
前記半導体基板の上部であって前記第2のウェル拡散層と離れた位置に形成され、前記第1のウェル拡散層とPN接合を形成する第2導電型の第3のウェル拡散層と、
前記第3のウェル拡散層の上部に形成された第2導電型のドレイン拡散層と、
前記第2のウェル拡散層、前記第1のウェル拡散層、および前記第3のウェル拡散層の上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成された前記ゲート電極と、
前記第3のウェル拡散層の上であって、前記ゲート絶縁膜に連設されるとともに、前記ゲート絶縁膜と前記ドレイン拡散層との間に形成された素子分離用絶縁膜と、
前記半導体基板のうち、前記第1のウェル拡散層および前記第3のウェル拡散層の底部に接する領域に形成された第1導電型の埋め込み拡散層とを備えている半導体装置。 - 素子分離用絶縁膜が形成された半導体基板の第1の領域に第1導電型の不純物イオンを選択的に注入して第1のウェル拡散層を形成する工程(a)と、
前記第1のウェル拡散層の少なくとも上部に第1導電型の不純物イオンを選択的に注入して第2のウェル拡散層を形成する工程(b)と、
前記半導体基板のうち前記第1の領域とは異なる第2の領域に第2導電型の不純物イオンを選択的に注入し、前記第1のウェルから間隔を空けた位置に第3のウェル拡散層を形成する工程(c)と、
前記半導体基板のうち、前記第1のウェル拡散層と前記第3のウェル拡散層との間であって、前記半導体基板の表面部から前記第3のウェル拡散層の不純物濃度分布の曲率ピーク位置よりも深い位置に至る領域に第2導電型のバッファ層を形成する工程(d)と、
第2導電型の不純物イオンを注入して前記第2のウェル拡散層、および前記第3のウェル拡散層の上にゲート絶縁膜とゲート電極とを順次形成する工程(e)と、
前記第2のウェル拡散層および前記第3のウェル拡散層の上部に第2導電型の不純物イオンを注入し、前記第2のウェル拡散層の上部にソース拡散層を形成するとともに、前記第3のウェル拡散層の上部にドレイン拡散層を形成する工程(f)とを備えている半導体装置の製造方法。 - 前記工程(d)では、第2導電型の不純物イオンを前記半導体基板に注入することによって前記バッファ層を形成することを特徴とする請求項9に記載の半導体装置の製造方法。
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US10529804B2 (en) * | 2017-08-21 | 2020-01-07 | Texas Instruments Incorporated | Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method |
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