JP2007073657A - 膜厚分布制御方法及び半導体装置の製造方法 - Google Patents
膜厚分布制御方法及び半導体装置の製造方法 Download PDFInfo
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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Abstract
【解決手段】 ISSGプロセスは、1%H2濃度で所定圧力下で行う第1の酸化処理と、5%H2濃度で同じ所定圧力下で行われる第2の酸化処理とを有し、第2の酸化処理を所定時間行うことで第1の酸化処理の膜厚分布のばらつきを補償する。酸化膜の最終膜厚と、第2の酸化処理における膜厚ばらつきの時間依存性と、第1及び第2の酸化処理における酸化膜の成膜速度とによって、第1及び第2の酸化処理の処理時間を決定する。
【選択図】 図2
Description
第1の酸化処理で形成される酸化膜の膜厚分布のばらつきを補償する第2の酸化処理の処理時間を決定するステップと、
酸化膜の最終膜厚と、前記決定した第2の酸化処理の処理時間と、第2の酸化処理における成膜速度とに基づいて、第2の酸化処理における下地膜厚を計算するステップと、
前記計算した下地膜厚と、第1の酸化処理における成膜速度とに基づいて、前記計算した下地膜厚を有する酸化膜を成膜するために必要な第1の酸化処理の処理時間を決定するステップとを有することを特徴とする。
第2の処理で形成される薄膜の膜厚分布の処理時間依存性に基づいて、第1の処理で形成される薄膜の膜厚分布のばらつきを補償する第2の処理の処理時間を決定するステップと、
薄膜の最終膜厚と、前記決定した第2の処理の処理時間と、第2の処理における成膜速度とに基づいて、第2の処理における下地膜厚を計算するステップと、
前記計算した下地膜厚と、第1の処理における成膜速度とに基づいて、前記計算した下地膜厚を有する薄膜を成膜するために必要な第1の処理の処理時間を決定するステップとを有することを特徴とする。
(1) 第1の酸化処理による膜厚ばらつきと、第2の酸化処理による膜厚ばらつきの双方の時間依存性から、第2の酸化処理における酸化時間を決定する。
(2)酸化膜の最終膜厚と、第2の酸化処理の酸化レートとから、第2の酸化処理を行なう前の下地膜厚を計算する。
(3) 第1の酸化処理の酸化レートから、第2の酸化処理を行なう前と同じ下地膜厚を第1の酸化処理で成膜するために必要な酸化時間を決定する。
Claims (6)
- 異なる膜厚分布が得られる第1の酸化処理と第2の酸化処理とを組み合わせた酸化処理によって酸化膜の膜厚分布を制御する、酸化膜の膜厚分布制御方法であって、
第1の酸化処理で形成される酸化膜の膜厚分布のばらつきを補償する第2の酸化処理の処理時間を決定するステップと、
酸化膜の最終膜厚と、前記決定した第2の酸化処理の処理時間と、第2の酸化処理における成膜速度とに基づいて、第2の酸化処理における下地膜厚を計算するステップと、
前記計算した下地膜厚と、第1の酸化処理における成膜速度とに基づいて、前記計算した下地膜厚を有する酸化膜を成膜するために必要な第1の酸化処理の処理時間を決定するステップとを有することを特徴とする膜厚分布制御方法。 - 前記処理時間を決定するステップでは、第2の酸化処理で形成される酸化膜の膜厚分布の処理時間依存性に基づいて前記処理時間を決定する、請求項1に記載の膜厚分布制御方法。
- 前記第1の酸化処理と前記第2の酸化処理とは、H2濃度が相互に異なるプロセスである、請求項1又は2に記載の膜厚分布制御方法。
- 前記第1の酸処理と前記第2の酸化処理とが同じ圧力下で行われる、請求項1〜3の何れか一に記載の膜厚分布制御方法。
- 請求項1〜4の何れか一に記載の膜厚分布制御方法を有することを特徴とする半導体装置の製造方法。
- 異なる膜厚分布が得られる第1の処理と第2の処理とを組み合わせたプロセスによって薄膜の膜厚分布を制御する、薄膜の膜厚分布制御方法であって、
第2の処理で形成される薄膜の膜厚分布の処理時間依存性に基づいて、第1の処理で形成される薄膜の膜厚分布のばらつきを補償する第2の処理の処理時間を決定するステップと、
薄膜の最終膜厚と、前記決定した第2の処理の処理時間と、第2の処理における成膜速度とに基づいて、第2の処理における下地膜厚を計算するステップと、
前記計算した下地膜厚と、第1の処理における成膜速度とに基づいて、前記計算した下地膜厚を有する薄膜を成膜するために必要な第1の処理の処理時間を決定するステップとを有することを特徴とする膜厚分布制御方法。
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US11/514,934 US7737048B2 (en) | 2005-09-06 | 2006-09-05 | Method for controlling thickness distribution of a film |
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CN110896022B (zh) * | 2018-09-13 | 2022-05-10 | 长鑫存储技术有限公司 | 半导体结构中氧化层的形成方法 |
TWI837126B (zh) * | 2019-05-03 | 2024-04-01 | 聯華電子股份有限公司 | 一種製作半導體元件的方法 |
CN112447497A (zh) * | 2019-08-28 | 2021-03-05 | 长鑫存储技术有限公司 | 氧化层形成方法、半导体器件的制作方法及半导体器件 |
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JP2002353214A (ja) * | 2001-05-24 | 2002-12-06 | Nec Corp | 半導体装置の製造方法 |
JP2002373984A (ja) * | 2001-06-14 | 2002-12-26 | Nec Corp | 半導体装置及び製造方法 |
JP2003086716A (ja) * | 2001-09-11 | 2003-03-20 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置及びその製造方法 |
JP2003163212A (ja) * | 2001-11-27 | 2003-06-06 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2003532290A (ja) * | 2000-04-27 | 2003-10-28 | アプライド マテリアルズ インコーポレイテッド | シリコン/金属複合膜堆積物を選択的に酸化するための方法及び装置 |
JP2005159266A (ja) * | 2003-11-25 | 2005-06-16 | Macronix Internatl Co Ltd | Ono構造上に酸化物を形成するための方法 |
JP2006128328A (ja) * | 2004-10-28 | 2006-05-18 | Renesas Technology Corp | 半導体装置及びその製造方法 |
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US6495805B2 (en) * | 2000-06-30 | 2002-12-17 | Tokyo Electron Limited | Method of determining set temperature trajectory for heat treatment system |
JP2003086713A (ja) | 2001-06-28 | 2003-03-20 | Matsushita Electric Ind Co Ltd | Sram装置 |
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JP2003532290A (ja) * | 2000-04-27 | 2003-10-28 | アプライド マテリアルズ インコーポレイテッド | シリコン/金属複合膜堆積物を選択的に酸化するための方法及び装置 |
JP2002353214A (ja) * | 2001-05-24 | 2002-12-06 | Nec Corp | 半導体装置の製造方法 |
JP2002373984A (ja) * | 2001-06-14 | 2002-12-26 | Nec Corp | 半導体装置及び製造方法 |
JP2003086716A (ja) * | 2001-09-11 | 2003-03-20 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置及びその製造方法 |
JP2003163212A (ja) * | 2001-11-27 | 2003-06-06 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2005159266A (ja) * | 2003-11-25 | 2005-06-16 | Macronix Internatl Co Ltd | Ono構造上に酸化物を形成するための方法 |
JP2006128328A (ja) * | 2004-10-28 | 2006-05-18 | Renesas Technology Corp | 半導体装置及びその製造方法 |
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