JP2005159266A - Ono構造上に酸化物を形成するための方法 - Google Patents
Ono構造上に酸化物を形成するための方法 Download PDFInfo
- Publication number
- JP2005159266A JP2005159266A JP2004079012A JP2004079012A JP2005159266A JP 2005159266 A JP2005159266 A JP 2005159266A JP 2004079012 A JP2004079012 A JP 2004079012A JP 2004079012 A JP2004079012 A JP 2004079012A JP 2005159266 A JP2005159266 A JP 2005159266A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- oxide
- flowing
- silicon nitride
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 95
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 79
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 70
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 45
- 239000001301 oxygen Substances 0.000 claims description 32
- 229910052760 oxygen Inorganic materials 0.000 claims description 32
- 230000003647 oxidation Effects 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- 239000007789 gas Substances 0.000 claims description 15
- 239000000203 mixture Substances 0.000 claims description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 14
- 239000001257 hydrogen Substances 0.000 claims description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000012159 carrier gas Substances 0.000 claims description 8
- 239000003795 chemical substances by application Substances 0.000 claims description 4
- 239000007800 oxidant agent Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 14
- 230000008569 process Effects 0.000 abstract description 65
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 238000000137 annealing Methods 0.000 abstract description 5
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- 230000015572 biosynthetic process Effects 0.000 description 23
- 235000012431 wafers Nutrition 0.000 description 21
- 238000010586 diagram Methods 0.000 description 17
- 150000004767 nitrides Chemical class 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 238000009279 wet oxidation reaction Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000003776 cleavage reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004774 atomic orbital Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004776 molecular orbital Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/954—Making oxide-nitride-oxide device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】第1酸化ケイ素層及び窒化ケイ素層を提供し;第1酸化ケイ素層及び窒化ケイ素層をパターン化し、部分的に完成したONOスタックのボトム酸化物及び窒化ケイ素部分を規定し、論理デバイス領域中の基板を露出させ;ラジカル酸化剤の存在下、急速熱アニーリングプロセスを行い、窒化ケイ素層の露出した表面上の第2酸化ケイ素層及び基板上のゲート酸化被膜を共存して形成し;完成したONOスタック及びゲート酸化物上に導電層を蒸着することによって形成される。
【選択図】図3
Description
本実施例において、パターン化されたSi表面及びSiN表面をウエア基板上に形成し、ウエハをISSG(in situ steam generation)炉内に置いた。ウエハをISSGチャンバ中で約950℃まで加熱し、キャリアガスとしてのN2中で、2slmのH2及び8slmのO2に約300秒間暴露し、Si上に約158Åの厚さの酸化物を形成し、SiN上に約128Åの厚さの酸化物を形成した。
本実施例において、ISSGプロセスを用いて、窒化ケイ素上の酸化物成長速度の実測値を、反応式から誘導される理論速度と比較する。
本実施例において、ISSGプロセスを用いて、850℃、900℃及び950℃の3種類の温度で、(DCS)窒化ケイ素上での酸化物成長速度を、シリコン基板上での酸化物成長速度と比較した。各温度でのウエハを、(H2/H2+O2)約33%(6slmのH2及び12slmのO2)の比率で流される水素及び酸素に暴露した。そして、酸化物の厚みを約30秒、60秒、90秒、及び120秒の時間間隔で測定した。
本実施例において、ISSGプロセスを用いて、(DCS)窒化ケイ素上の酸化物成長速度を、約25%及び約33%の2種類の異なる水素及び酸素比率(H2/H2+O2)、850℃、900℃、及び950℃の3種類の温度で比較し、酸化物の厚みを約30秒、60秒、90秒、及び120秒の時間間隔で測定した。窒化ケイ素膜を、XT(ランプ型)シングルウエハチャンバを用いて調製した。一般的に、高い加工温度で成長して得られた酸化物は、各時間間隔でさらに厚く、すなわち、酸化物形成速度は、温度が高いほど大きかった。明らかに、酸素ラジカルの運動エネルギーが増加することにより、活性化障壁をさらに容易に超えることが可能である。また、各々の加工温度で、酸化物形成速度は、H2/H2+O2比が大きいほど大きかった。すなわち、所与の加工温度について、特定の酸化物の厚みに到達するための加工時間は、水素濃度が高いほど短い。明らかに、水素濃度が高くなるほど、分子状酸素の反応性酸素ラジカルへの開裂が促進され、反応に利用可能な酸素ラジカルが多くなる。
本実施例において、酸化物を、種々の方法によって形成した窒化物上に、850℃及び950℃でISSGによって成長させた。上記の窒化物は、DCSベースの窒化物(XTランプ型チャンバ)、(XTランプ型)シングルウエハチャンバによって成長させたシランベースの窒化物、及びSiNGenシングルウエハチャンバシステムによって成長させたシランベースの窒化物を含む。予想されるように、トップ酸化物の成長速度は、温度が高いほど大きかった。2種類の温度それぞれについて、成長速度は、3種類の膜タイプ全てで実質的に同じであった。
Claims (23)
- ONO構造を形成するための方法であって、
酸化物−窒化物膜を基板表面上に提供する工程であって、前記酸化物−窒化物膜が前記基板上の第1酸化被膜及び前記第1酸化被膜上の窒化ケイ素層を含む、工程と、
前記基板上のONOスタックのボトム酸化物及び窒化ケイ素部分を規定するために前記酸化物−窒化物膜をパターン化する工程であって、前記ボトム酸化物及び窒化ケイ素部分が露出した側壁を有し、かつ前記窒化ケイ素部分が露出した表面を有する、工程と、
前記露出した側壁及び前記露出した表面を、ラジカル酸化剤を含む雰囲気中で急速熱酸化に暴露し、前記露出した表面上及び前記パターン化された窒化ケイ素部分の側壁上及び前記パターン化されたボトム酸化物部分の側壁上に、酸化被膜を形成する工程とを含む方法。 - 前記ラジカル酸化剤は、酸素ラジカルを含む、請求項1に記載の方法。
- 前記ラジカル酸化剤はO・を含む、請求項1に記載の方法。
- 前記暴露する工程は、前記基板を選択された温度まで加熱する工程と、前記露出した側壁及び前記露出した表面を、選択された圧力で選択された時間、酸素を含有するガス及び水素を含有するガスの混合物に選択された比率で暴露する工程とを含み、ここで、前記酸素を含有するガス及び前記水素を含有するガスの成分が反応して、前記加熱された基板の近くで前記ラジカル酸化剤を生成する、請求項1に記載の方法。
- 前記基板を加熱する工程は、前記基板を約700℃〜約1300℃の範囲の温度まで加熱する工程を含む、請求項4に記載の方法。
- 前記基板を加熱する工程は、前記基板を約900℃〜約1150℃の範囲の温度まで加熱する工程を含む、請求項4に記載の方法。
- 前記基板を加熱する工程は、前記基板を約850℃〜約1000℃の範囲の温度まで加熱する工程を含む、請求項4に記載の方法。
- 前記暴露する工程は、前記基板を選択された温度まで加熱する工程と、前記露出した側壁及び前記露出した表面を、選択された圧力で選択された時間、O2及びH2の混合物に選択された比率で暴露する工程を含み、ここで、前記O2及びH2の成分が反応して、前記加熱された基板の近くでO・を生成する、請求項1に記載の方法。
- 前記暴露する工程は前記基板を約700℃〜約1300℃の範囲の温度まで加熱する工程、前記露出した側壁及び前記露出した表面を、約1torr〜約20torrの範囲の圧力で、約1〜1000秒の範囲の時間、O2及びH2の混合物に約0.1%〜約40%(H2/H2+O2)の範囲の比率で暴露する工程を含む、請求項8に記載の方法。
- 前記加熱する工程は、前記基板を約900℃〜約1150℃の範囲の温度まで加熱する工程を含む、請求項9に記載の方法。
- 前記基板を加熱する工程は、前記基板を約850℃〜約1000℃の範囲の温度まで加熱する工程を含む、請求項9に記載の方法。
- 前記暴露する工程は、前記加熱された基板の上を、O2及びH2の混合物を約5%〜約33%(H2/H2+O2)の比率で流す工程を含む、請求項9に記載の方法。
- 前記暴露する工程は、前記加熱された基板の上を、O2及びH2の混合物を約1:19〜約1:2(H2:O2)の範囲の比率で流す工程を含む、請求項9に記載の方法。
- 前記暴露する工程は、O2及びH2の前記混合物を、前記加熱された基板の上を約10秒〜約500秒の範囲の時間流す工程を含む、請求項9に記載の方法。
- 前記暴露する工程は、O2及びH2の前記混合物を、前記加熱された基板の上を約30秒〜約300秒の範囲の時間流す工程を含む、請求項9に記載の方法。
- 前記暴露する工程は、前記基板を炉中で加熱する工程と、前記炉内にO2及びH2の混合物を、選択された圧力及び選択された時間で、選択された比率で流す工程とを含み、ここで、前記O2及びH2の成分が反応して、前記加熱された基板の近くでO・を生成する、請求項1に記載の方法。
- O2及びH2の前記混合物を流す工程は、キャリアガスを流す工程をさらに含む、請求項16に記載の方法。
- O2及びH2の前記混合物を流す工程は、キャリアガスとしてN2を流す工程をさらに含む、請求項17に記載の方法。
- O2及びH2の前記混合物を選択された比率で流す工程は、選択された比率の流速で前記O2及びH2を流す工程を含む、請求項16に記載の方法。
- O2及びH2の前記混合物を流す工程は、選択された流速でキャリアガスとしてN2を流す工程をさらに含む、請求項19に記載の方法。
- O2及びH2を流す工程は、約1〜約40slmの範囲の混合された流速でO2及びH2を流す工程を含む、請求項19に記載の方法。
- 前記O2及びH2を流す工程は、約1〜約40slmの範囲の混合された流速でO2及びH2を流す工程を含み、N2を流す工程は、約50slmまでの流速でN2を流す工程を含む、請求項20に記載の方法。
- 酸化ケイ素/窒化ケイ素/酸化ケイ素構造を有するメモリセルであって、
基板内の埋込みドレイン及び埋込みソースと;
前記埋込みドレイン上の埋込みドレイン酸化被膜及び前記埋込みソース上の埋込みソース酸化被膜と;
前記埋込みドレインと前記埋込みソースとの間に配置される前記基板の領域を覆い、かつ前記埋込みドレイン酸化被膜の一部分及び前記埋込みソース酸化被膜の一部分を覆う、第1酸化ケイ素層と;
前記第1酸化ケイ素層の一部分を覆う窒化ケイ素層と;
前記窒化ケイ素層を完全に覆い、かつ前記第1酸化ケイ素層と接触する第2酸化ケイ素層と;
前記第2酸化ケイ素層上のゲート導電層と
を備えるメモリセル。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/721,605 US7183166B2 (en) | 2003-11-25 | 2003-11-25 | Method for forming oxide on ONO structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005159266A true JP2005159266A (ja) | 2005-06-16 |
JP4598421B2 JP4598421B2 (ja) | 2010-12-15 |
Family
ID=34591835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004079012A Expired - Fee Related JP4598421B2 (ja) | 2003-11-25 | 2004-03-18 | Ono構造上に酸化物を形成するための方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7183166B2 (ja) |
JP (1) | JP4598421B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007073657A (ja) * | 2005-09-06 | 2007-03-22 | Elpida Memory Inc | 膜厚分布制御方法及び半導体装置の製造方法 |
JP2009267366A (ja) * | 2008-04-02 | 2009-11-12 | Nec Electronics Corp | 半導体記憶装置及びその製造方法 |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7910429B2 (en) * | 2004-04-07 | 2011-03-22 | Promos Technologies, Inc. | Method of forming ONO-type sidewall with reduced bird's beak |
US7297597B2 (en) * | 2004-07-23 | 2007-11-20 | Promos Technologies, Inc. | Method for simultaneously fabricating ONO-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using ISSG |
US7785965B2 (en) * | 2006-09-08 | 2010-08-31 | Spansion Llc | Dual storage node memory devices and methods for fabricating the same |
US20080150002A1 (en) | 2006-12-22 | 2008-06-26 | Jeong-Mo Hwang | Simultaneous Formation of a Top Oxide Layer in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Transistor and a Gate Oxide in a Metal Oxide Semiconductor (MOS) |
JP2008227403A (ja) * | 2007-03-15 | 2008-09-25 | Spansion Llc | 半導体装置およびその製造方法 |
US9299568B2 (en) | 2007-05-25 | 2016-03-29 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
US8614124B2 (en) | 2007-05-25 | 2013-12-24 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
US20090061608A1 (en) * | 2007-08-29 | 2009-03-05 | Merchant Tushar P | Method of forming a semiconductor device having a silicon dioxide layer |
US7754545B2 (en) * | 2007-12-03 | 2010-07-13 | Macronix International Co., Ltd. | Semiconductor device and method of fabricating the same |
US9431549B2 (en) | 2007-12-12 | 2016-08-30 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a high dielectric constant blocking region |
US8252653B2 (en) | 2008-10-21 | 2012-08-28 | Applied Materials, Inc. | Method of forming a non-volatile memory having a silicon nitride charge trap layer |
US8198671B2 (en) * | 2009-04-22 | 2012-06-12 | Applied Materials, Inc. | Modification of charge trap silicon nitride with oxygen plasma |
US9102522B2 (en) | 2009-04-24 | 2015-08-11 | Cypress Semiconductor Corporation | Method of ONO integration into logic CMOS flow |
US8071453B1 (en) * | 2009-04-24 | 2011-12-06 | Cypress Semiconductor Corporation | Method of ONO integration into MOS flow |
JP2010263119A (ja) * | 2009-05-08 | 2010-11-18 | Panasonic Corp | 不揮発性半導体記憶装置及びその製造方法 |
US8541273B2 (en) | 2010-09-23 | 2013-09-24 | Globalfoundries Singapore Pte. Ltd. | Dielectric stack |
US8993457B1 (en) | 2014-02-06 | 2015-03-31 | Cypress Semiconductor Corporation | Method of fabricating a charge-trapping gate stack using a CMOS process flow |
CN109309123B (zh) * | 2017-07-28 | 2020-11-10 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN108054080B (zh) * | 2017-11-30 | 2019-11-01 | 武汉新芯集成电路制造有限公司 | 一种于衬底上获得热氧化层的方法 |
US20220037479A1 (en) * | 2020-08-03 | 2022-02-03 | Changxin Memory Technologies, Inc. | Oxide layer, semiconductor structure, and manufacturing methods therefor |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH098152A (ja) * | 1995-06-20 | 1997-01-10 | Sony Corp | 半導体記憶装置の製造方法 |
JPH09205157A (ja) * | 1995-11-20 | 1997-08-05 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
JPH10163338A (ja) * | 1996-11-28 | 1998-06-19 | Ricoh Co Ltd | 半導体装置とその製造方法 |
JP2000353741A (ja) * | 1999-06-11 | 2000-12-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002353214A (ja) * | 2001-05-24 | 2002-12-06 | Nec Corp | 半導体装置の製造方法 |
WO2003007359A1 (en) * | 2001-07-13 | 2003-01-23 | International Business Machines Corporation | Method of improving gate activation by employing atomic oxygen oxidation |
JP2004092918A (ja) * | 2002-08-29 | 2004-03-25 | Toshiba Kyaria Kk | 空気調和機 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4949154A (en) | 1983-02-23 | 1990-08-14 | Texas Instruments, Incorporated | Thin dielectrics over polysilicon |
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
US6187640B1 (en) * | 1998-11-17 | 2001-02-13 | Fujitsu Limited | Semiconductor device manufacturing method including various oxidation steps with different concentration of chlorine to form a field oxide |
US6297096B1 (en) * | 1997-06-11 | 2001-10-02 | Saifun Semiconductors Ltd. | NROM fabrication method |
US5966603A (en) | 1997-06-11 | 1999-10-12 | Saifun Semiconductors Ltd. | NROM fabrication method with a periphery portion |
US5861347A (en) * | 1997-07-03 | 1999-01-19 | Motorola Inc. | Method for forming a high voltage gate dielectric for use in integrated circuit |
US6159866A (en) | 1998-03-02 | 2000-12-12 | Applied Materials, Inc. | Method for insitu vapor generation for forming an oxide on a substrate |
US6037273A (en) | 1997-07-11 | 2000-03-14 | Applied Materials, Inc. | Method and apparatus for insitu vapor generation |
US6074917A (en) | 1998-06-16 | 2000-06-13 | Advanced Micro Devices, Inc. | LPCVD oxide and RTA for top oxide of ONO film to improve reliability for flash memory devices |
US6383861B1 (en) * | 1999-02-18 | 2002-05-07 | Micron Technology, Inc. | Method of fabricating a dual gate dielectric |
JP3229294B2 (ja) * | 1999-06-04 | 2001-11-19 | キヤノン販売株式会社 | 被成膜面の改質方法及び半導体装置の製造方法 |
US6171911B1 (en) | 1999-09-13 | 2001-01-09 | Taiwan Semiconductor Manufacturing Company | Method for forming dual gate oxides on integrated circuits with advanced logic devices |
US6117730A (en) * | 1999-10-25 | 2000-09-12 | Advanced Micro Devices, Inc. | Integrated method by using high temperature oxide for top oxide and periphery gate oxide |
US6184155B1 (en) | 2000-06-19 | 2001-02-06 | Taiwan Semiconductor Manufacturing Company | Method for forming a ultra-thin gate insulator layer |
TW494541B (en) * | 2001-05-28 | 2002-07-11 | Macronix Int Co Ltd | Method for producing silicon nitride read-only-memory |
KR100407573B1 (ko) * | 2001-08-09 | 2003-11-28 | 삼성전자주식회사 | 부유 트랩형 비휘발성 메모리 장치 형성 방법 |
US20030040189A1 (en) * | 2001-08-22 | 2003-02-27 | Ping-Yi Chang | Shallow trench isolation fabrication |
JP3745297B2 (ja) * | 2002-03-27 | 2006-02-15 | Necエレクトロニクス株式会社 | 不揮発性半導体記憶装置の製造方法 |
KR100493022B1 (ko) * | 2002-07-10 | 2005-06-07 | 삼성전자주식회사 | Sonos 구조를 갖는 불휘발성 메모리 소자의 제조 방법 |
JP2004095918A (ja) * | 2002-08-30 | 2004-03-25 | Fasl Japan Ltd | 半導体記憶装置及び半導体装置の製造方法 |
TW575945B (en) * | 2002-12-17 | 2004-02-11 | Nanya Technology Corp | Method for fabricating a vertical NROM cell |
US20040203253A1 (en) * | 2003-04-14 | 2004-10-14 | June-Min Yao | Method of forming a dielectric layer |
US7202523B2 (en) * | 2003-11-17 | 2007-04-10 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
US7297597B2 (en) * | 2004-07-23 | 2007-11-20 | Promos Technologies, Inc. | Method for simultaneously fabricating ONO-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using ISSG |
US6946349B1 (en) * | 2004-08-09 | 2005-09-20 | Chartered Semiconductor Manufacturing Ltd. | Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses |
US7232724B1 (en) * | 2005-04-25 | 2007-06-19 | Advanced Micro Devices, Inc. | Radical oxidation for bitline oxide of SONOS |
-
2003
- 2003-11-25 US US10/721,605 patent/US7183166B2/en not_active Expired - Lifetime
-
2004
- 2004-03-18 JP JP2004079012A patent/JP4598421B2/ja not_active Expired - Fee Related
-
2007
- 2007-01-19 US US11/625,177 patent/US7919372B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH098152A (ja) * | 1995-06-20 | 1997-01-10 | Sony Corp | 半導体記憶装置の製造方法 |
JPH09205157A (ja) * | 1995-11-20 | 1997-08-05 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
JPH10163338A (ja) * | 1996-11-28 | 1998-06-19 | Ricoh Co Ltd | 半導体装置とその製造方法 |
JP2000353741A (ja) * | 1999-06-11 | 2000-12-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002353214A (ja) * | 2001-05-24 | 2002-12-06 | Nec Corp | 半導体装置の製造方法 |
WO2003007359A1 (en) * | 2001-07-13 | 2003-01-23 | International Business Machines Corporation | Method of improving gate activation by employing atomic oxygen oxidation |
JP2004535077A (ja) * | 2001-07-13 | 2004-11-18 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 原子状酸素促進酸化(atomicoxygenenhancedoxidation)を使ってゲート活性化を改良する方法 |
JP2004092918A (ja) * | 2002-08-29 | 2004-03-25 | Toshiba Kyaria Kk | 空気調和機 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007073657A (ja) * | 2005-09-06 | 2007-03-22 | Elpida Memory Inc | 膜厚分布制御方法及び半導体装置の製造方法 |
JP4507108B2 (ja) * | 2005-09-06 | 2010-07-21 | エルピーダメモリ株式会社 | 膜厚分布制御方法及び半導体装置の製造方法 |
JP2009267366A (ja) * | 2008-04-02 | 2009-11-12 | Nec Electronics Corp | 半導体記憶装置及びその製造方法 |
US8063435B2 (en) | 2008-04-02 | 2011-11-22 | Renesas Electronics Corporation | Semiconductor memory and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US20070117353A1 (en) | 2007-05-24 |
US20050110102A1 (en) | 2005-05-26 |
US7919372B2 (en) | 2011-04-05 |
US7183166B2 (en) | 2007-02-27 |
JP4598421B2 (ja) | 2010-12-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4598421B2 (ja) | Ono構造上に酸化物を形成するための方法 | |
US7683455B2 (en) | Semiconductor device and method of manufacturing thereof | |
JP2005197643A (ja) | フラッシュセメモリ素子の製造方法 | |
US20060270157A1 (en) | Method of manufacturing flash memory device | |
US6100160A (en) | Oxide etch barrier formed by nitridation | |
US6261973B1 (en) | Remote plasma nitridation to allow selectively etching of oxide | |
JP2004214608A (ja) | 半導体素子の製造方法 | |
JP3383807B2 (ja) | 半導体装置の製造方法 | |
KR100271399B1 (ko) | 반도체 소자 분리를 위한 얕은 트랜치 제조 방법 | |
US5946588A (en) | Low temperature sub-atmospheric ozone oxidation process for making thin gate oxides | |
KR20060022345A (ko) | 반도체 장치의 제조 방법 | |
KR100475025B1 (ko) | 반도체소자의 소자분리절연막 형성방법 | |
TW533473B (en) | Manufacturing method of shallow trench isolation | |
US5977608A (en) | Modified poly-buffered isolation | |
US7670954B2 (en) | Method of manufacturing semiconductor device | |
KR100245081B1 (ko) | 반도체 소자의 소자분리절연막 형성방법 | |
US20020081811A1 (en) | Low-temperature deposition of silicon nitride/oxide stack | |
KR100336567B1 (ko) | 반도체장치의소자분리방법 | |
CN114843176B (zh) | 一种半导体结构的制造方法 | |
KR100881736B1 (ko) | 반도체 소자의 제조방법 | |
JPH118317A (ja) | 半導体装置およびその製造方法 | |
JPH10335500A (ja) | 半導体装置の製造方法 | |
KR100240273B1 (ko) | 반도체 소자의 필드 산화막 형성 방법 | |
KR100262017B1 (ko) | 셀 제조방법 | |
TW388103B (en) | Method of forming field oxide layer with double sidewall layer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070214 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091007 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20091112 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091209 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100601 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100823 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100913 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100924 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4598421 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131001 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |