JP2006121004A - パワーic - Google Patents
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- JP2006121004A JP2006121004A JP2004309940A JP2004309940A JP2006121004A JP 2006121004 A JP2006121004 A JP 2006121004A JP 2004309940 A JP2004309940 A JP 2004309940A JP 2004309940 A JP2004309940 A JP 2004309940A JP 2006121004 A JP2006121004 A JP 2006121004A
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- H01L23/367—Cooling facilitated by shape of device
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- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Semiconductor Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】並列接続される複数個のパワー素子からなるパワー部と、パワー素子の制御回路を構成する制御回路部とが、半導体基板1の表層部に隣接して配置されたパワーIC100であって、層間絶縁膜1a,1bを介して、パワー部の直上に、パワー素子の外部電極であるパワーメタル20a〜20dが形成され、パワーメタル20a〜20dが、制御回路部の直上に拡張されてなるパワーIC100とする。
【選択図】 図2
Description
従来のパワーIC90においては、主としてチップ1の裏面側に接続されたヒートシンク4から放熱を行っていた。しかしながら、シリコン(Si)からなるチップ1は熱抵抗が高く、放熱性をさらに高めるためには、チップ1の主面側からも効率的に放熱させる必要がある。
1,10 半導体基板
1a,1b 層間絶縁膜
10a 埋め込み酸化膜
10b 絶縁分離トレンチ
10c 層間絶縁膜
10f フィールドグランド領域
2a〜2d,20a〜20d,21a,21b,22a〜22d,23a〜23d,24 パワーメタル
24f 埋め込み金属
3 制御回路部のパッド
3i 島状メタル
4 ヒートシンク
5 ワイヤ
6 半田ボール
200 プリント基板
Claims (10)
- 並列接続される複数個のパワー素子からなるパワー部と、前記パワー素子の制御回路を構成する制御回路部とが、半導体基板の表層部に隣接して配置されたパワーICであって、
層間絶縁膜を介して、前記パワー部の直上に、前記パワー素子の外部電極であるパワーメタルが形成され、
前記パワーメタルが、前記制御回路部の直上に拡張されてなることを特徴とするパワーIC。 - 前記パワーメタルが、前記パワー部をほぼ覆ってなることを特徴とする請求項1に記載のパワーIC。
- 前記パワーメタルが、前記制御回路部をほぼ覆ってなることを特徴とする請求項1または2に記載のパワーIC。
- 前記パワー素子が、MOS型トランジスタであり、
前記パワーメタルが、前記MOS型トランジスタにおけるソースもしくはドレインの外部電極であることを特徴とする請求項1乃至3のいずれか一項に記載のパワーIC。 - 前記パワーメタルに、複数本のワイヤがボンディングされてなることを特徴とする請求項1乃至4のいずれか一項に記載のパワーIC。
- 前記パワーメタルが、複数個の半田ボールを介して、プリント基板の配線に接続されてなることを特徴とする請求項1乃至4のいずれか一項に記載のパワーIC。
- 前記制御回路が、カレントミラー回路を有してなり、
前記パワーメタルが、前記制御回路部における前記カレントミラー回路を構成する部分の直上を除いて、前記制御回路部の直上に拡張されてなることを特徴とする請求項1乃至6のいずれか一項に記載のパワーIC。 - 前記カレントミラー回路を構成する部分の直上に、
前記パワーメタルに連結していない島状メタルが配置されてなることを特徴とする請求項7に記載のパワーIC。 - 前記半導体基板が、埋め込み酸化膜を有するSOI構造の半導体基板であり、
前記パワー部と制御回路部とが、絶縁分離トレンチにより絶縁分離されてなり、
前記制御回路部の周りに、前記絶縁分離トレンチに囲まれ、素子が形成されていないフィールドグランド領域が形成されてなり、
前記パワーメタルが、前記制御回路部の周りにおいて、前記層間絶縁膜に形成されたビアホール内の埋め込み金属を介して、前記フィールドグランド領域に接続されてなることを特徴とする請求項1乃至8のいずれか一項に記載のパワーIC。 - 前記パワーメタルの材質が、アルミニウムもしくは銅であることを特徴とする請求項1乃至9のいずれか一項に記載のパワーIC。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004309940A JP4687066B2 (ja) | 2004-10-25 | 2004-10-25 | パワーic |
US11/251,776 US20060086449A1 (en) | 2004-10-25 | 2005-10-18 | Semiconductor device having element portion and control circuit portion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004309940A JP4687066B2 (ja) | 2004-10-25 | 2004-10-25 | パワーic |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006121004A true JP2006121004A (ja) | 2006-05-11 |
JP4687066B2 JP4687066B2 (ja) | 2011-05-25 |
Family
ID=36205113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004309940A Expired - Fee Related JP4687066B2 (ja) | 2004-10-25 | 2004-10-25 | パワーic |
Country Status (2)
Country | Link |
---|---|
US (1) | US20060086449A1 (ja) |
JP (1) | JP4687066B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008311410A (ja) * | 2007-06-14 | 2008-12-25 | Denso Corp | 半導体装置 |
JP2009260215A (ja) * | 2008-03-25 | 2009-11-05 | Toshiba Corp | 半導体装置 |
US9887239B2 (en) | 2010-06-07 | 2018-02-06 | Micron Technology, Inc. | Memory arrays |
JP2020149994A (ja) * | 2019-03-11 | 2020-09-17 | ローム株式会社 | 半導体装置 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005042706B4 (de) * | 2005-09-01 | 2008-08-14 | Atmel Germany Gmbh | Halbleiter-Chip zur Erzeugung einer steuerbaren Frequenz |
JP4858290B2 (ja) * | 2006-06-05 | 2012-01-18 | 株式会社デンソー | 負荷駆動装置 |
US9059083B2 (en) * | 2007-09-14 | 2015-06-16 | Infineon Technologies Ag | Semiconductor device |
JP4924685B2 (ja) * | 2009-09-23 | 2012-04-25 | 株式会社デンソー | 半導体装置及びその製造方法 |
US9995890B2 (en) * | 2010-09-27 | 2018-06-12 | Finisar Corporation | Thermal management of a locker etalon in a transmitter optical subassembly |
WO2013118222A1 (ja) * | 2012-02-07 | 2013-08-15 | 富士電機株式会社 | 電力変換装置 |
CN105161436B (zh) | 2015-09-11 | 2018-05-22 | 柯全 | 倒装芯片的封装方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0766402A (ja) * | 1993-08-23 | 1995-03-10 | Fuji Electric Co Ltd | 半導体装置 |
JP2000299927A (ja) * | 1999-02-14 | 2000-10-24 | Yazaki Corp | 電力供給系 |
JP2002368218A (ja) * | 2001-06-08 | 2002-12-20 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5192989A (en) * | 1989-11-28 | 1993-03-09 | Nissan Motor Co., Ltd. | Lateral dmos fet device with reduced on resistance |
JP3355817B2 (ja) * | 1994-10-20 | 2002-12-09 | 株式会社デンソー | 半導体装置 |
JP2997179B2 (ja) * | 1995-01-27 | 2000-01-11 | モトローラ株式会社 | パワーmosトランジスタ |
JP3435930B2 (ja) * | 1995-09-28 | 2003-08-11 | 株式会社デンソー | 半導体装置及びその製造方法 |
JP4239310B2 (ja) * | 1998-09-01 | 2009-03-18 | ソニー株式会社 | 半導体装置の製造方法 |
US6365932B1 (en) * | 1999-08-20 | 2002-04-02 | Denso Corporation | Power MOS transistor |
JP2001085625A (ja) * | 1999-09-13 | 2001-03-30 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6624484B2 (en) * | 2001-07-31 | 2003-09-23 | Nokia Corporation | IGFET and tuning circuit |
JP3809168B2 (ja) * | 2004-02-03 | 2006-08-16 | 株式会社東芝 | 半導体モジュール |
-
2004
- 2004-10-25 JP JP2004309940A patent/JP4687066B2/ja not_active Expired - Fee Related
-
2005
- 2005-10-18 US US11/251,776 patent/US20060086449A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0766402A (ja) * | 1993-08-23 | 1995-03-10 | Fuji Electric Co Ltd | 半導体装置 |
JP2000299927A (ja) * | 1999-02-14 | 2000-10-24 | Yazaki Corp | 電力供給系 |
JP2002368218A (ja) * | 2001-06-08 | 2002-12-20 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008311410A (ja) * | 2007-06-14 | 2008-12-25 | Denso Corp | 半導体装置 |
JP2009260215A (ja) * | 2008-03-25 | 2009-11-05 | Toshiba Corp | 半導体装置 |
US9887239B2 (en) | 2010-06-07 | 2018-02-06 | Micron Technology, Inc. | Memory arrays |
JP2020149994A (ja) * | 2019-03-11 | 2020-09-17 | ローム株式会社 | 半導体装置 |
JP7290960B2 (ja) | 2019-03-11 | 2023-06-14 | ローム株式会社 | 半導体装置 |
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Publication number | Publication date |
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JP4687066B2 (ja) | 2011-05-25 |
US20060086449A1 (en) | 2006-04-27 |
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