JP2005183952A - 導電孔を有したプリント回路ボードの製造方法及びボード - Google Patents
導電孔を有したプリント回路ボードの製造方法及びボード Download PDFInfo
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- H—ELECTRICITY
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
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- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
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- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0969—Apertured conductors
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
【解決手段】プリント回路ボードの製造方法であって、導電貫通孔はボード構造の二つの誘電層内に形成されており、指定された導電層を接続するようになっている。一つの孔は二つの隣接する層を、他方の孔は二つの隣接する層を接続し、他方の孔に接続された導電層の一方を含んでいる。一つあるいはそれ以上の数の孔を用いて3つ全ての導電層を接続することもできる。結果としての孔は、金属メッキや導電・非導電ペーストで充填されることができる。後者の場合、ボードの外表面上のペーストに例えばパッド等のトップカバー導電層を提供することもできる。
【選択図】図6
Description
13 第2導電層
15 第2導電層
17・19 開口部
21・21′ ランド部分
23 第2誘電層
25・27・29 孔
31・33 追加孔
41 導電層
43 導電コーティング
50 上面部
61 ペースト
63 導電層
71 銅材料
81 ハンダボール
83 積層チップキャリア
85 導電パッド
91・97 追加誘電層
93 導電面
95 導電貫通孔
99・101 貫通孔
103 平面導電層
Claims (20)
- 多層プリント回路ボードの製造方法であって、
第1面及び反対側の第2面を有する第1誘電層を形成するステップと、
該第1誘電層の該第1面上に第1導電層を形成するステップと、
該第1誘電層の前記第2面上に少なくとも一つの開口部を含んだ第2導電層を形成するステップと、
該第1誘電層の該第2面上の該第2導電層上に第1面と第2面とを有した第2誘電層であって、該第2誘電層の該第1面は少なくとも一つの開口部を含んだ前記第2導電層の少なくとも一部と接触している第2誘電層を形成するステップと、
一方は前記第2導電層にだけ延び下り、他方は前記第2導電層内の少なくとも1つの前記開口部を通過して前記第1導電層へと延び下る少なくとも二つの孔を前記第2誘電層内に形成するステップと、
該第2誘電層の前記第2面上に第3導電層を形成するステップと、
前記第1導電層と前記第2導電層を前記孔の前記一方上の前記導電コーティングと電気的にカップリングさせ、前記第2導電層と前記第3導電層を前記孔の前記他方上の導電コーティングと電気的にカップリングさせるために、前記少なくとも二つの孔の表面上に導電コーティングを形成するステップと、
を含んでいることを特徴とする多層プリント回路ボードの製造方法。 - 第2導電層も電気的に第3導電層とカップリングさせるように、該第2導電層は少なくとも二つの孔上の導電コーティングのそれぞれと電気的にカップリングされていることを特徴とする請求項1記載の方法。
- 導電コーティングを有する少なくとも二つの孔のそれぞれを導電材料で充填するステップをさらに含んでいることを特徴とする請求項1記載の方法。
- 充填ステップははメッキ加工ステップを含んでいることを特徴とする請求項3記載の方法。
- 充填ステップは少なくとも二つの孔をペーストで充填するステップを含んでいることを特徴とする請求項3記載の方法。
- ペーストは電気導電性であることを特徴とする請求項5記載の方法 。
- 該ペーストは非電気導電性であることを特徴とする請求項5記載の方法。
- 少なくとも二つの孔のそれぞれ内でペースト上に導電層をメッキするステップをさらに含んでいることを特徴とする請求項5記載の方法。
- 第1導電層、第2導電層及び第3導電層はフォトリトグラフステップで形成されることを特徴とする請求項1記載の方法。
- 少なくとも二つの孔はレーザーを使用して形成されることを特徴とする請求項1記載の方法。
- 導電層は少なくとも二つの孔のそれぞれの上にメッキ加工ステップで形成されることを特徴とする請求項1記載の方法。
- 第2誘電層は第2導電層の上に積層加工ステップで形成されることを特徴とする請求項1記載の方法。
- 多層プリント回路ボードであって、
第1面及び反対側の第2面を有する第1誘電層と、
該第1誘電層の該第1面上に形成された第1導電層と、
該第1誘電層の前記第2面上に形成され、少なくとも一つの開口部を含んだ第2導電層と、
該第1誘電層の前記第2面上の該第2導電層上に形成された第1面と第2面を有する第2誘電層と、
を含んでおり、該第2誘電層の該第1面は、前記少なくとも一つの開口部上を含んで該第2導電層の少なくとも一部と接触しており、前記第2誘電層は、少なくとも二つのレーザー加工孔を含んでおり、該レーザー加工孔の一方は前記第2導電層にだけ延び下っており、前記他方のレーザー加工孔は該第2導電層の前記少なくとも一つの開口部を通過して前記第1導電層にまで延び下っており、
本回路ボードはさらに、
前記第2誘電層の前記第2面上に形成された第3導電層と、
前記第1導電層と前記第2導電層を前記レーザー加工孔の前記一方上の前記導電コーティングと電気的にカップリングさせ、前記第2導電層と前記第3導電層を前記レーザー加工孔の前記他方上の導電コーティングと電気的にカップリングさせるように、該少なくとも二つのレーザー加工孔の表面上に形成された導電コーティングと、
を含んでいることを特徴とする多層プリント回路ボード。 - 第2導電層も第3導電層と電気的にカップリングさせるように、該第2導電層は少なくとも二つのレーザー加工孔上の導電コーティングのそれぞれと電気的にカップリングされていることを特徴とする請求項13記載の多層プリント回路ボード。
- 導電コーティングを有した少なくとも二つのレーザー加工孔のそれぞれは、該レーザー充填された孔を実質的に充填する充填材を含んでいることを特徴とする請求項13記載の多層プリント回路ボード。
- 充填材はペーストであることを特徴とする請求項15記載の多層プリント回路ボード。
- ペーストは導電性であることを特徴とする請求項16記載の多層プリント回路ボード。
- ペーストは非導電性であることを特徴とする請求項16記載の多層プリント回路ボード。
- 充填材はメッキ加工された導電性材料であることを特徴とする請求項15記載の多層プリント回路ボード。
- 多層プリント回路ボードの製造方法であって、
第1面と反対側の第2面とを有しており、該第1面と該第2面にそれぞれ第1導電層と、少なくとも一つの開口部を有した第2導電層とを有した回路基板を形成するステップと、
前記第2導電層を実質的に覆うように該回路基板に該第2誘電層を積層するステップと、
一方は前記第2導電層にのみ延び下り、他方は該第2導電層内の前記少なくとも一つの開口部を通過して前記第1導電層に延び下る少なくとも二つの孔を前記第2誘電層内に形成するステップと、
第3導電層を該第2誘電層の前記第2面に形成するステップと、
前記第1導電層と前記第2導電層を前記孔の前記一方上の前記導電コーティングと電気的にカップリングさせ、前記第2導電層と前記第3導電層を前記孔の前記他方上の前記導電コーティングと電気的にカップリングさせるように、該少なくとも二つの孔の表面上に導電コーティングを形成するステップと、
を含んでいることを特徴とする多層プリント回路ボードの製造方法。
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US10/737,974 US7211289B2 (en) | 2003-12-18 | 2003-12-18 | Method of making multilayered printed circuit board with filled conductive holes |
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Also Published As
Publication number | Publication date |
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US7211289B2 (en) | 2007-05-01 |
US20050136646A1 (en) | 2005-06-23 |
US20060121722A1 (en) | 2006-06-08 |
US20060183316A1 (en) | 2006-08-17 |
EP1545175A3 (en) | 2007-05-30 |
TWI355871B (en) | 2012-01-01 |
US7348677B2 (en) | 2008-03-25 |
EP1545175A2 (en) | 2005-06-22 |
TW200524502A (en) | 2005-07-16 |
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