IT1271946B - Dispositivo di memoria a semiconduttore con struttura a tripla zona a pozzetto - Google Patents

Dispositivo di memoria a semiconduttore con struttura a tripla zona a pozzetto

Info

Publication number
IT1271946B
IT1271946B ITMI930230A ITMI930230A IT1271946B IT 1271946 B IT1271946 B IT 1271946B IT MI930230 A ITMI930230 A IT MI930230A IT MI930230 A ITMI930230 A IT MI930230A IT 1271946 B IT1271946 B IT 1271946B
Authority
IT
Italy
Prior art keywords
type
conductivity
group
power
wells
Prior art date
Application number
ITMI930230A
Other languages
English (en)
Inventor
Dong-Jae Lee
Dong-Sun Min
Dong-Soo Jun
Yong-Sik Seok
Original Assignee
Samsung Electronics Co Ltd
Modiano Guido
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd, Modiano Guido filed Critical Samsung Electronics Co Ltd
Publication of ITMI930230A0 publication Critical patent/ITMI930230A0/it
Publication of ITMI930230A1 publication Critical patent/ITMI930230A1/it
Application granted granted Critical
Publication of IT1271946B publication Critical patent/IT1271946B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Un dispositivo e smiconduttore con una regione della matrice a cella di memoria e una regione del circuito periferico integrate in un substrato di conduttività del primo tipo che comprende un primo gruppo di piazzuole o pad di alimentazione per alimentare solamente la regione della matrice a cella di memoria, un secondo gruppo di pad di alimentazione per alimentare solamente la regione del circuito periferico, un terzo gruppo di pad di alimentazione per alimentare solo la plu-ralità di linee di parola e le memorie temporanee o buffer di ingresso TTL, un terzo gruppo di pad di alimentazione per alimentare solo gli elementi di comando di uscita dei dati, primi well di conduttività del secondo tipo con almeno primi well di conduttività del primo tipo formati nella regione della matrice a cella di memoria e collegati con il primo gruppo di pad di alimentazione, secondi well del secondo tipo di conduttività con almeno primi well del primo tipo di conduttivitá formati nella regione del circuito periferico e collegati con il secondo gruppo di pad di alimentazione, una prima pluralità di transistori MOS del secondo tipo di conduttività formati nei primi well del primo tipo di conduttività e collegati con il terzo gruppo di pad di alimentazione e una seconda pluralità di transistori MOS del secondo tipo di conduttività formati nei secondi well del primo tipo di conduttività e collegati con il quarto gruppo di pad di alimentazione.
ITMI930230A 1992-07-13 1993-02-10 Dispositivo di memoria a semiconduttore con struttura a tripla zona a pozzetto IT1271946B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920012438A KR940003026A (ko) 1992-07-13 1992-07-13 트리플웰을 이용한 반도체장치

Publications (3)

Publication Number Publication Date
ITMI930230A0 ITMI930230A0 (it) 1993-02-10
ITMI930230A1 ITMI930230A1 (it) 1994-08-10
IT1271946B true IT1271946B (it) 1997-06-10

Family

ID=19336233

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI930230A IT1271946B (it) 1992-07-13 1993-02-10 Dispositivo di memoria a semiconduttore con struttura a tripla zona a pozzetto

Country Status (7)

Country Link
JP (1) JPH0685200A (it)
KR (1) KR940003026A (it)
DE (1) DE4300826A1 (it)
FR (1) FR2693587A1 (it)
GB (1) GB2269049A (it)
IT (1) IT1271946B (it)
TW (1) TW210402B (it)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3002371B2 (ja) 1993-11-22 2000-01-24 富士通株式会社 半導体装置とその製造方法
US5595925A (en) * 1994-04-29 1997-01-21 Texas Instruments Incorporated Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein
WO1995035572A1 (en) 1994-06-20 1995-12-28 Neomagic Corporation Graphics controller integrated circuit without memory interface
JP4037470B2 (ja) 1994-06-28 2008-01-23 エルピーダメモリ株式会社 半導体装置
US5696721A (en) * 1995-05-05 1997-12-09 Texas Instruments Incorporated Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range
JPH0955483A (ja) * 1995-06-09 1997-02-25 Mitsubishi Electric Corp 半導体記憶装置
TW328641B (en) * 1995-12-04 1998-03-21 Hitachi Ltd Semiconductor integrated circuit device and process for producing the same
US6750527B1 (en) 1996-05-30 2004-06-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having a plurality of wells, test method of testing the semiconductor integrated circuit device, and test device which executes the test method
JP4534163B2 (ja) * 1997-06-16 2010-09-01 エルピーダメモリ株式会社 半導体集積回路装置
JP4014708B2 (ja) 1997-08-21 2007-11-28 株式会社ルネサステクノロジ 半導体集積回路装置の設計方法
KR100275725B1 (ko) * 1997-12-27 2000-12-15 윤종용 트리플웰 구조를 갖는 반도체 메모리 장치 및 그 제조방법
JP2000101045A (ja) * 1998-07-23 2000-04-07 Mitsubishi Electric Corp 半導体装置
JP2001291779A (ja) * 2000-04-05 2001-10-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
WO2003003461A1 (fr) * 2001-06-27 2003-01-09 Renesas Technology Corp. Dispositif de circuit integre a semiconducteur et procede de reduction du bruit
US6930930B2 (en) 2002-11-06 2005-08-16 Infineon Technologies Ag Using isolated p-well transistor arrangements to avoid leakage caused by word line/bit line shorts
TWI256724B (en) * 2003-08-06 2006-06-11 Sanyo Electric Co Semiconductor device
KR100571650B1 (ko) 2005-03-31 2006-04-17 주식회사 하이닉스반도체 저전압용 반도체 메모리 장치
DE102005030372A1 (de) * 2005-06-29 2007-01-04 Infineon Technologies Ag Vorrichtung und Verfahren zur Regelung der Schwellspannung eines Transistors, insbesondere eines Transistors eines Leseverstärkers eines Halbleiter- Speicherbauelements
JP4967478B2 (ja) * 2006-06-30 2012-07-04 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP5022643B2 (ja) * 2006-07-13 2012-09-12 株式会社東芝 半導体装置のｅｓｄ保護回路
KR100817417B1 (ko) * 2006-12-26 2008-03-27 동부일렉트로닉스 주식회사 고전압 씨모스 소자 및 그 제조 방법
JP5104377B2 (ja) * 2008-02-15 2012-12-19 セイコーエプソン株式会社 電圧安定化装置
KR101610829B1 (ko) 2009-12-15 2016-04-11 삼성전자주식회사 트리플 웰 구조를 가지는 플래시 메모리 소자
KR101585616B1 (ko) 2009-12-16 2016-01-15 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11251148B2 (en) * 2020-01-28 2022-02-15 Micron Technology, Inc. Semiconductor devices including array power pads, and associated semiconductor device packages and systems

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62155555A (ja) * 1985-09-18 1987-07-10 Sony Corp 相補型ｍｏｓトランジスタ
DE3900769A1 (de) * 1989-01-12 1990-08-09 Fraunhofer Ges Forschung Integrierte schaltung mit zumindest einem n-kanal-fet und zumindest einem p-kanal-fet
US5157281A (en) * 1991-07-12 1992-10-20 Texas Instruments Incorporated Level-shifter circuit for integrated circuits

Also Published As

Publication number Publication date
ITMI930230A0 (it) 1993-02-10
KR940003026A (ko) 1994-02-19
TW210402B (en) 1993-08-01
GB2269049A (en) 1994-01-26
ITMI930230A1 (it) 1994-08-10
JPH0685200A (ja) 1994-03-25
DE4300826A1 (de) 1994-01-20
GB9304655D0 (en) 1993-04-28
FR2693587A1 (fr) 1994-01-14

Similar Documents

Publication Publication Date Title
IT1271946B (it) Dispositivo di memoria a semiconduttore con struttura a tripla zona a pozzetto
CN100383968C (zh) 层迭式半导体存储器件
TW200609940A (en) Semiconductor integrated circuit device
AU2461597A (en) Layout for a semiconductor memory device having redundant elements
JPH06350052A (ja) 半導体記憶装置
JP2006202485A5 (it)
IT1256497B (it) Memoria di sola lettura programmabile e cancellabile elettricamente con un circuito di verifica e correzzione dell'errore
EP1184876A3 (en) Semiconductor memory
EP0908887A3 (en) Semiconductor integrated circuit device
AU6945700A (en) Circuit and method for a multiplexed redundancy scheme in a memory device
TW267254B (en) Semiconductor memory with hierarchical bit lines
KR930018582A (ko) 반도체 메모리장치의 비트라인 분리클럭 저너레이터
KR880000968A (ko) 반도체 기억장치
EP0908886A3 (en) Semiconductor integrated circuit device
JPS59155954A (ja) 半導体メモリ装置
TW371345B (en) Nonvolatile semiconductor memory
US6788600B2 (en) Non-volatile semiconductor memory
KR970003208A (ko) 고속동작을 위한 회로 배치 구조를 가지는 반도체 메모리 장치
KR950009073B1 (ko) 반도체 메모리 소자
IT8322952A1 (it) Memoria ad accesso casuale di tipo mos
KR100299948B1 (ko) 반도체집적회로장치
IT1258816B (it) Disposizione di una schiera di celle ridondanti per un dispositivo di memoria a semiconduttore
IT1245152B (it) Cella dram avente una struttura sagomata a tunnel e procedimento di formazione di essa
US6169699B1 (en) Semiconductor memory device
EP0883131A3 (en) Semiconductor storage device such as cache memory

Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960429