IT1256497B - Memoria di sola lettura programmabile e cancellabile elettricamente con un circuito di verifica e correzzione dell'errore - Google Patents

Memoria di sola lettura programmabile e cancellabile elettricamente con un circuito di verifica e correzzione dell'errore

Info

Publication number
IT1256497B
IT1256497B ITMI922999A ITMI922999A IT1256497B IT 1256497 B IT1256497 B IT 1256497B IT MI922999 A ITMI922999 A IT MI922999A IT MI922999 A ITMI922999 A IT MI922999A IT 1256497 B IT1256497 B IT 1256497B
Authority
IT
Italy
Prior art keywords
bit lines
page memories
correction
circuit
readable memory
Prior art date
Application number
ITMI922999A
Other languages
English (en)
Inventor
Jin-Ki Kim
Original Assignee
Samsung Elecctronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Elecctronics Co Ltd filed Critical Samsung Elecctronics Co Ltd
Publication of ITMI922999A0 publication Critical patent/ITMI922999A0/it
Publication of ITMI922999A1 publication Critical patent/ITMI922999A1/it
Application granted granted Critical
Publication of IT1256497B publication Critical patent/IT1256497B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Ciò che viene divulgato è una EEPROM che comprende una matrice di memoria includente una pluralità di linee di bit, una pluralità di celle di memoria collegate rispettivamente alle linee di bit e alle celle di parità e un circuito di verifica e di correzione dell'errore con una porta di colonna collegata alla pluralità di linee di bit per caricare i dati di ingresso nelle rispettive memorie temporanee o intermedie di pagina e per elaborare i dati della memoria in unità a byte multipli dei dati di ingresso in modo da generare i dati di parità che consistono in una pluralità di bit scritti in modo casuale nelle memorie temporanee di pagina, in cui le memorie temporanee di pagina sono collegate tra la pluralità di linee di bit e la porta di colonna. Vengono forniti preferibilmente mezzi di separazione per controllare il collegamento tra le memorie temporanee di pagina e la pluralità di linee di bit.
ITMI922999A 1992-03-30 1992-12-31 Memoria di sola lettura programmabile e cancellabile elettricamente con un circuito di verifica e correzzione dell'errore IT1256497B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920005284A KR950003013B1 (ko) 1992-03-30 1992-03-30 틀림정정회로를 가지는 이이피롬

Publications (3)

Publication Number Publication Date
ITMI922999A0 ITMI922999A0 (it) 1992-12-31
ITMI922999A1 ITMI922999A1 (it) 1994-07-01
IT1256497B true IT1256497B (it) 1995-12-07

Family

ID=19331104

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI922999A IT1256497B (it) 1992-03-30 1992-12-31 Memoria di sola lettura programmabile e cancellabile elettricamente con un circuito di verifica e correzzione dell'errore

Country Status (9)

Country Link
US (1) US5448578A (it)
JP (1) JP2525112B2 (it)
KR (1) KR950003013B1 (it)
CN (1) CN1035698C (it)
DE (1) DE4242810C2 (it)
FR (1) FR2689295B1 (it)
GB (1) GB2265738B (it)
IT (1) IT1256497B (it)
TW (1) TW272286B (it)

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KR100266748B1 (ko) 1997-12-31 2000-10-02 윤종용 반도체 메모리 장치 및 그 장치의 에러 정정 방법
JP4074029B2 (ja) 1999-06-28 2008-04-09 株式会社東芝 フラッシュメモリ
FR2809222A1 (fr) * 2000-05-17 2001-11-23 St Microelectronics Sa Memoire eeprom comprenant un systeme de correction d'erreur
JP3595495B2 (ja) 2000-07-27 2004-12-02 Ｎｅｃマイクロシステム株式会社 半導体記憶装置
US7042770B2 (en) * 2001-07-23 2006-05-09 Samsung Electronics Co., Ltd. Memory devices with page buffer having dual registers and method of using the same
KR100543447B1 (ko) * 2003-04-03 2006-01-23 삼성전자주식회사 에러정정기능을 가진 플래쉬메모리장치
US7099221B2 (en) 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20060010339A1 (en) 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US7116602B2 (en) 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US6965537B1 (en) 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
KR100680486B1 (ko) * 2005-03-30 2007-02-08 주식회사 하이닉스반도체 향상된 동작 성능을 가지는 플래시 메모리 장치의 페이지버퍼 회로 및 그 독출 및 프로그램 동작 제어 방법
JP2008059711A (ja) * 2006-09-01 2008-03-13 Toshiba Corp 半導体記憶装置
US7836386B2 (en) * 2006-09-27 2010-11-16 Qimonda Ag Phase shift adjusting method and circuit
JP5016888B2 (ja) * 2006-10-04 2012-09-05 株式会社東芝 不揮発性半導体記憶装置
US7894289B2 (en) 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
KR100799018B1 (ko) * 2006-12-27 2008-01-28 주식회사 하이닉스반도체 불휘발성 메모리 소자 및 자기 보상 방법
KR100888482B1 (ko) 2007-05-11 2009-03-12 삼성전자주식회사 비휘발성 반도체 메모리 장치 및 상기 비휘발성 반도체메모리 장치의 쓰기 방법
KR101678404B1 (ko) * 2010-02-25 2016-11-23 삼성전자주식회사 사전 확률 정보를 사용하는 메모리 시스템 및 그것의 데이터 처리 방법
JP2010231887A (ja) * 2010-07-20 2010-10-14 Toshiba Corp 不揮発性半導体メモリ
US9047953B2 (en) * 2013-08-22 2015-06-02 Macronix International Co., Ltd. Memory device structure with page buffers in a page-buffer level separate from the array level
US9484113B2 (en) * 2014-04-15 2016-11-01 Advanced Micro Devices, Inc. Error-correction coding for hot-swapping semiconductor devices
KR20160125745A (ko) * 2015-04-22 2016-11-01 에스케이하이닉스 주식회사 반도체 장치

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Also Published As

Publication number Publication date
US5448578A (en) 1995-09-05
CN1077049A (zh) 1993-10-06
TW272286B (it) 1996-03-11
JPH05298895A (ja) 1993-11-12
GB9227139D0 (en) 1993-02-24
JP2525112B2 (ja) 1996-08-14
KR930020472A (ko) 1993-10-19
ITMI922999A1 (it) 1994-07-01
GB2265738A (en) 1993-10-06
CN1035698C (zh) 1997-08-20
GB2265738B (en) 1996-01-17
FR2689295A1 (fr) 1993-10-01
KR950003013B1 (ko) 1995-03-29
DE4242810C2 (de) 2000-06-08
FR2689295B1 (fr) 1996-12-27
DE4242810A1 (de) 1993-10-07
ITMI922999A0 (it) 1992-12-31

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