IT1265147B1 - Dispositivo di memoria a semicondutttore avente modalita' di prova e metodo di settaggio della modalita' di prova - Google Patents
Dispositivo di memoria a semicondutttore avente modalita' di prova e metodo di settaggio della modalita' di provaInfo
- Publication number
- IT1265147B1 IT1265147B1 IT93MI001529A ITMI931529A IT1265147B1 IT 1265147 B1 IT1265147 B1 IT 1265147B1 IT 93MI001529 A IT93MI001529 A IT 93MI001529A IT MI931529 A ITMI931529 A IT MI931529A IT 1265147 B1 IT1265147 B1 IT 1265147B1
- Authority
- IT
- Italy
- Prior art keywords
- test mode
- memory device
- semiconductor memory
- control signals
- memory cell
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000000034 method Methods 0.000 title 1
- 239000011159 matrix material Substances 0.000 abstract 2
- 230000004044 response Effects 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
Un dispositivo di memoria a semiconduttore secondo la presente invenzione include una matrice a celle di memoria (1), circuiti interni (2-13) per la lettura e la scrittura di dati della matrice a celle di memoria, un controllore della modalità di prova (14) e circuiti di resettaggio dell'accensione (17-19). Il controllore della modalità di prova setta una modalità di prova della matrice a celle di memoria in risposta ad una predeterminata struttura di cambiamento di livelli logici di almeno diversi segnali di controllo tra una pluralità di segnali di controllo per controllare i circuiti interni. I circuiti di resettaggio dell'accensione settano il controllore della modalità di prova in uno stato iniziale durante un periodo variabile che viene definito in base ad una temporizzazione di cambio di un livello logico di un segnale di controllo che determina una temporizzazione di settaggio della modalità di prova tra gli almeno diversi segnali di controllo, in risposta all'accensione. Come risultato, è possibile impedire che il dispositivo di memoria a semiconduttore entri in modo errato nella modalità di prova provocata da un rumore o simile dopo l'accensione.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4186610A JPH0636593A (ja) | 1992-07-14 | 1992-07-14 | 半導体記憶装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI931529A0 ITMI931529A0 (it) | 1993-07-12 |
ITMI931529A1 ITMI931529A1 (it) | 1995-01-12 |
IT1265147B1 true IT1265147B1 (it) | 1996-10-31 |
Family
ID=16191591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT93MI001529A IT1265147B1 (it) | 1992-07-14 | 1993-07-12 | Dispositivo di memoria a semicondutttore avente modalita' di prova e metodo di settaggio della modalita' di prova |
Country Status (5)
Country | Link |
---|---|
US (1) | US5365481A (it) |
JP (1) | JPH0636593A (it) |
KR (1) | KR970006221B1 (it) |
DE (1) | DE4322994C2 (it) |
IT (1) | IT1265147B1 (it) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0459001B1 (de) * | 1990-05-31 | 1996-01-24 | Siemens Aktiengesellschaft | Integrierter Halbleiterspeicher |
SG49632A1 (en) * | 1993-10-26 | 1998-06-15 | Intel Corp | Programmable code store circuitry for a nonvolatile semiconductor memory device |
KR960008824B1 (en) * | 1993-11-17 | 1996-07-05 | Samsung Electronics Co Ltd | Multi bit test circuit and method of semiconductor memory device |
US5526311A (en) * | 1993-12-30 | 1996-06-11 | Intel Corporation | Method and circuitry for enabling and permanently disabling test mode access in a flash memory device |
US6587978B1 (en) | 1994-02-14 | 2003-07-01 | Micron Technology, Inc. | Circuit and method for varying a pulse width of an internal control signal during a test mode |
US5831918A (en) | 1994-02-14 | 1998-11-03 | Micron Technology, Inc. | Circuit and method for varying a period of an internal control signal during a test mode |
JPH08153400A (ja) * | 1994-11-29 | 1996-06-11 | Mitsubishi Electric Corp | Dram |
US5991214A (en) * | 1996-06-14 | 1999-11-23 | Micron Technology, Inc. | Circuit and method for varying a period of an internal control signal during a test mode |
US6115307A (en) | 1997-05-19 | 2000-09-05 | Micron Technology, Inc. | Method and structure for rapid enablement |
JPH1116395A (ja) * | 1997-06-25 | 1999-01-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP3180728B2 (ja) * | 1997-07-25 | 2001-06-25 | 日本電気株式会社 | 半導体記憶装置 |
IT1296908B1 (it) * | 1997-12-29 | 1999-08-02 | Sgs Thomson Microelectronics | Metodo e relativo circuito per regolare la durata di un segnale di sincronismo atd per temporizzare l'accesso ad una memoria non-volatile |
JPH11353900A (ja) | 1998-06-11 | 1999-12-24 | Mitsubishi Electric Corp | 半導体装置 |
JP3292145B2 (ja) * | 1998-06-26 | 2002-06-17 | 日本電気株式会社 | 半導体記憶装置 |
JP3987674B2 (ja) * | 2000-06-01 | 2007-10-10 | 富士通株式会社 | 半導体集積回路 |
JP4790925B2 (ja) * | 2001-03-30 | 2011-10-12 | 富士通セミコンダクター株式会社 | アドレス発生回路 |
JP4338548B2 (ja) * | 2004-02-26 | 2009-10-07 | Okiセミコンダクタ株式会社 | パワーオンリセット回路および半導体集積回路 |
KR100824777B1 (ko) * | 2007-02-07 | 2008-04-24 | 삼성전자주식회사 | 로우 경로와 칼럼 경로에 대해 다른 초기화 시점을 가지는반도체 메모리 장치 및 반도체 메모리 장치의 초기화 방법 |
KR100857448B1 (ko) * | 2007-06-11 | 2008-09-10 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 리셋펄스 생성회로 |
KR20100005610A (ko) * | 2008-07-07 | 2010-01-15 | 주식회사 하이닉스반도체 | 반도체 메모리 디바이스의 테스트모드 제어 회로 및 방법 |
US8069385B1 (en) * | 2008-07-14 | 2011-11-29 | T-Ram Semiconductor, Inc. | Programmable built-in self-test architecture |
JP4856208B2 (ja) * | 2009-03-30 | 2012-01-18 | 株式会社東芝 | 半導体装置 |
KR101646910B1 (ko) * | 2011-01-11 | 2016-08-09 | 페어차일드코리아반도체 주식회사 | 파워 온 리셋 회로를 포함하는 반도체 소자 |
KR20120087720A (ko) * | 2011-01-28 | 2012-08-07 | 에스케이하이닉스 주식회사 | 상변화 메모리 장치 |
US9213063B2 (en) | 2014-03-26 | 2015-12-15 | Freescale Semiconductor, Inc. | Reset generation circuit for scan mode exit |
WO2018227399A1 (zh) | 2017-06-13 | 2018-12-20 | 深圳市汇顶科技股份有限公司 | 光学生物识别模组、显示装置以及电子设备 |
EP3480608B1 (en) | 2017-09-19 | 2021-01-13 | Shenzhen Goodix Technology Co., Ltd. | Method and system for measuring power-on reset time |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2624654B2 (ja) * | 1986-10-15 | 1997-06-25 | 株式会社東芝 | パワーオンリセツト回路 |
JPH0229118A (ja) * | 1988-05-27 | 1990-01-31 | Advanced Micro Devices Inc | Cmosパワーオン・リセット回路 |
JP2568455B2 (ja) * | 1990-08-16 | 1997-01-08 | 三菱電機株式会社 | 半導体記憶装置 |
US5134586A (en) * | 1990-08-17 | 1992-07-28 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with chip enable control from output enable during test mode |
US5134587A (en) * | 1990-08-17 | 1992-07-28 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with automatic test mode exit on chip enable |
JPH04119600A (ja) * | 1990-09-10 | 1992-04-21 | Mitsubishi Electric Corp | テストモード機能内蔵ダイナミックランダムアクセスメモリ装置 |
-
1992
- 1992-07-14 JP JP4186610A patent/JPH0636593A/ja not_active Withdrawn
-
1993
- 1993-07-09 KR KR1019930012938A patent/KR970006221B1/ko not_active IP Right Cessation
- 1993-07-09 DE DE4322994A patent/DE4322994C2/de not_active Expired - Fee Related
- 1993-07-09 US US08/088,641 patent/US5365481A/en not_active Expired - Fee Related
- 1993-07-12 IT IT93MI001529A patent/IT1265147B1/it active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
US5365481A (en) | 1994-11-15 |
ITMI931529A0 (it) | 1993-07-12 |
KR970006221B1 (ko) | 1997-04-24 |
KR940003039A (ko) | 1994-02-19 |
ITMI931529A1 (it) | 1995-01-12 |
DE4322994C2 (de) | 1996-01-11 |
JPH0636593A (ja) | 1994-02-10 |
DE4322994A1 (de) | 1994-01-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
IT1265147B1 (it) | Dispositivo di memoria a semicondutttore avente modalita' di prova e metodo di settaggio della modalita' di prova | |
CN1926637B (zh) | 非易失性存储器及其编程方法 | |
US4055754A (en) | Memory device and method of testing the same | |
US5608679A (en) | Fast internal reference cell trimming for flash EEPROM memory | |
US8233329B2 (en) | Architecture and method for memory programming | |
US7444458B2 (en) | Method for assigning addresses to memory devices | |
KR100217215B1 (ko) | 내장 기록 기능을 갖는 플래시 메모리를 끼워넣은 마이크로컴퓨터 | |
TW263562B (en) | Wafer burn-in test circuit of a semiconductor memory device | |
TW343307B (en) | Nonvolatile memory system and nonvolatile semiconductor memory | |
DE19807298A1 (de) | Synchrone Halbleiterspeichereinrichtung | |
WO2002103706A3 (en) | System and method for identification of faulty or weak memory cells under simulated extreme operating conditions | |
US6081870A (en) | Method and apparatus to achieve fast suspend in flash memories | |
US11615838B2 (en) | Programming memory cells at two different levels in parallel | |
US6076177A (en) | Method and apparatus for testing a circuit module concurrently with a non-volatile memory operation in a multi-module data processing system | |
WO2002103522A3 (en) | System and method for built in self repair of memories using speed stress test | |
US6064603A (en) | Non-volatile semiconductor storage device | |
US4502131A (en) | Electrically programmable memory matrix | |
US5619454A (en) | Programming method for healing over-erased cells for a flash memory device | |
DE69922818D1 (de) | Verfahren und schaltung zum blockweisen beschreiben von speichern mit breitem datenbus | |
JPS62501807A (ja) | ブ−スト語ラインを有する半導体メモリ | |
JPH0793040B2 (ja) | 書込み・消去可能な読出し専用メモリ | |
US6385110B1 (en) | Multilevel non-volatile semiconductor memory device | |
US6781884B2 (en) | System for setting memory voltage threshold | |
US5946256A (en) | Semiconductor memory having data transfer between RAM array and SAM array | |
US5652721A (en) | Testing an integrated circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970730 |