DE69522545D1 - Halbleiterspeicheranordnung mit eingebauten Redundanzspeicherzellen - Google Patents

Halbleiterspeicheranordnung mit eingebauten Redundanzspeicherzellen

Info

Publication number
DE69522545D1
DE69522545D1 DE69522545T DE69522545T DE69522545D1 DE 69522545 D1 DE69522545 D1 DE 69522545D1 DE 69522545 T DE69522545 T DE 69522545T DE 69522545 T DE69522545 T DE 69522545T DE 69522545 D1 DE69522545 D1 DE 69522545D1
Authority
DE
Germany
Prior art keywords
built
redundancy
memory cells
semiconductor memory
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69522545T
Other languages
English (en)
Other versions
DE69522545T2 (de
Inventor
Sumio Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69522545D1 publication Critical patent/DE69522545D1/de
Application granted granted Critical
Publication of DE69522545T2 publication Critical patent/DE69522545T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/806—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by reducing size of decoders
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/0016—Arrangements providing connection between exchanges
    • H04Q3/0029—Provisions for intelligent networking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE69522545T 1994-11-29 1995-11-28 Halbleiterspeicheranordnung mit eingebauten Redundanzspeicherzellen Expired - Lifetime DE69522545T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6294412A JPH08153399A (ja) 1994-11-29 1994-11-29 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69522545D1 true DE69522545D1 (de) 2001-10-11
DE69522545T2 DE69522545T2 (de) 2002-04-18

Family

ID=17807423

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69522545T Expired - Lifetime DE69522545T2 (de) 1994-11-29 1995-11-28 Halbleiterspeicheranordnung mit eingebauten Redundanzspeicherzellen

Country Status (5)

Country Link
US (1) US5570318A (de)
EP (1) EP0718767B1 (de)
JP (1) JPH08153399A (de)
KR (1) KR0184920B1 (de)
DE (1) DE69522545T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4766961B2 (ja) * 1995-05-12 2011-09-07 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR0157344B1 (ko) * 1995-05-25 1998-12-01 김광호 반도체 메모리 장치의 퓨즈소자 회로
JP3557019B2 (ja) * 1995-11-17 2004-08-25 株式会社東芝 半導体記憶装置
JP2882369B2 (ja) * 1996-06-27 1999-04-12 日本電気株式会社 半導体記憶装置
CA2202692C (en) * 1997-04-14 2006-06-13 Mosaid Technologies Incorporated Column redundancy in semiconductor memories
US6191983B1 (en) 1997-06-19 2001-02-20 Hitachi, Ltd. Semiconductor memory
US5867433A (en) * 1997-07-11 1999-02-02 Vanguard International Semiconductor Corporation Semiconductor memory with a novel column decoder for selecting a redundant array
KR100282226B1 (ko) * 1998-06-24 2001-02-15 김영환 반도체 메모리의 구제회로
US6208569B1 (en) * 1999-04-06 2001-03-27 Genesis Semiconductor, Inc. Method of and apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device
JP2001101890A (ja) * 1999-09-28 2001-04-13 Mitsubishi Electric Corp 半導体記憶装置
KR100572758B1 (ko) * 2000-11-02 2006-04-24 (주)이엠엘에스아이 로우 리던던시 리페어 효율을 증가시키는 반도체 메모리장치
KR101062740B1 (ko) * 2008-12-26 2011-09-06 주식회사 하이닉스반도체 퓨즈 박스 및 이를 구비한 반도체 집적 회로 장치
KR101177968B1 (ko) * 2009-03-04 2012-08-28 에스케이하이닉스 주식회사 고집적 반도체 장치를 위한 퓨즈

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6150294A (ja) * 1984-08-18 1986-03-12 Mitsubishi Electric Corp 半導体記憶装置の冗長回路
JPS62217498A (ja) * 1986-03-06 1987-09-24 Fujitsu Ltd 半導体記憶装置
JPS6427100A (en) * 1987-07-23 1989-01-30 Matsushita Electric Ind Co Ltd Semiconductor memory device with redundant circuit
US5265055A (en) * 1988-10-07 1993-11-23 Hitachi, Ltd. Semiconductor memory having redundancy circuit
JPH02208898A (ja) * 1989-02-08 1990-08-20 Seiko Epson Corp 半導体記憶装置
JPH0317898A (ja) * 1989-06-14 1991-01-25 Matsushita Electron Corp 半導体記憶装置
US5485418A (en) * 1990-01-16 1996-01-16 Mitsubishi Denki Kabushiki Kaisha Associative memory
KR930003164A (ko) * 1991-07-26 1993-02-24 김광호 반도체메모리 리던던시 장치
JP2853406B2 (ja) * 1991-09-10 1999-02-03 日本電気株式会社 半導体記憶装置
KR950015041B1 (ko) * 1992-11-23 1995-12-21 삼성전자주식회사 로우리던던시회로를 가지는 고집적 반도체 메모리 장치
KR950004623B1 (ko) * 1992-12-07 1995-05-03 삼성전자주식회사 리던던시 효율이 향상되는 반도체 메모리 장치
JP2856645B2 (ja) * 1993-09-13 1999-02-10 株式会社東芝 半導体記憶装置
JPH07176200A (ja) * 1993-12-17 1995-07-14 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
KR0184920B1 (ko) 1999-04-15
KR960019313A (ko) 1996-06-17
EP0718767B1 (de) 2001-09-05
DE69522545T2 (de) 2002-04-18
JPH08153399A (ja) 1996-06-11
US5570318A (en) 1996-10-29
EP0718767A1 (de) 1996-06-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP