KR960008845A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

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Publication number
KR960008845A
KR960008845A KR1019950028054A KR19950028054A KR960008845A KR 960008845 A KR960008845 A KR 960008845A KR 1019950028054 A KR1019950028054 A KR 1019950028054A KR 19950028054 A KR19950028054 A KR 19950028054A KR 960008845 A KR960008845 A KR 960008845A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
semiconductor
memory
Prior art date
Application number
KR1019950028054A
Other languages
English (en)
Other versions
KR100221940B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR960008845A publication Critical patent/KR960008845A/ko
Application granted granted Critical
Publication of KR100221940B1 publication Critical patent/KR100221940B1/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1019950028054A 1994-08-31 1995-08-31 반도체기억장치 KR100221940B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP94-207344 1994-08-31
JP20734494 1994-08-31
JP16987295A JP3469362B2 (ja) 1994-08-31 1995-07-05 半導体記憶装置
JP95-169872 1995-07-05

Publications (2)

Publication Number Publication Date
KR960008845A true KR960008845A (ko) 1996-03-22
KR100221940B1 KR100221940B1 (ko) 1999-09-15

Family

ID=26493081

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950028054A KR100221940B1 (ko) 1994-08-31 1995-08-31 반도체기억장치

Country Status (3)

Country Link
US (1) US5949101A (ko)
JP (1) JP3469362B2 (ko)
KR (1) KR100221940B1 (ko)

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JP4065572B2 (ja) 1997-03-28 2008-03-26 株式会社ルネサステクノロジ 半導体装置
JP3583583B2 (ja) * 1997-07-08 2004-11-04 株式会社東芝 半導体装置及びその製造方法
JP3011152B2 (ja) * 1997-10-01 2000-02-21 日本電気株式会社 半導体記憶装置の製造方法および半導体記憶装置
JP3540640B2 (ja) 1998-12-22 2004-07-07 株式会社東芝 不揮発性半導体記憶装置
JP2001168306A (ja) * 1999-12-09 2001-06-22 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US6424569B1 (en) 2000-02-25 2002-07-23 Advanced Micro Devices, Inc. User selectable cell programming
US6219276B1 (en) 2000-02-25 2001-04-17 Advanced Micro Devices, Inc. Multilevel cell programming
US6205055B1 (en) 2000-02-25 2001-03-20 Advanced Micro Devices, Inc. Dynamic memory cell programming voltage
US6297988B1 (en) 2000-02-25 2001-10-02 Advanced Micro Devices, Inc. Mode indicator for multi-level memory
US6707713B1 (en) 2000-03-01 2004-03-16 Advanced Micro Devices, Inc. Interlaced multi-level memory
KR100338783B1 (en) * 2000-10-28 2002-06-01 Samsung Electronics Co Ltd Semiconductor device having expanded effective width of active region and fabricating method thereof
US6835987B2 (en) * 2001-01-31 2004-12-28 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device in which selection gate transistors and memory cells have different structures
US6894343B2 (en) * 2001-05-18 2005-05-17 Sandisk Corporation Floating gate memory cells utilizing substrate trenches to scale down their size
US6936887B2 (en) * 2001-05-18 2005-08-30 Sandisk Corporation Non-volatile memory cells utilizing substrate trenches
KR100598092B1 (ko) * 2001-05-18 2006-07-07 삼성전자주식회사 플래시 메모리 및 그 형성 방법
KR100395759B1 (ko) * 2001-07-21 2003-08-21 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조방법
US6894930B2 (en) 2002-06-19 2005-05-17 Sandisk Corporation Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND
KR101110191B1 (ko) * 2002-06-19 2012-02-15 쌘디스크 코포레이션 스케일 낸드용 인접셀들 사이의 크로스 커플링을 실드하기위한 딥 워드라인 트렌치
JP3917063B2 (ja) 2002-11-21 2007-05-23 株式会社東芝 半導体装置及びその製造方法
JP4875284B2 (ja) * 2003-03-06 2012-02-15 スパンション エルエルシー 半導体記憶装置およびその製造方法
JP2005085996A (ja) * 2003-09-09 2005-03-31 Toshiba Corp 半導体装置及びその製造方法
JP3966850B2 (ja) * 2003-11-20 2007-08-29 株式会社東芝 半導体装置およびその製造方法
JP2005332885A (ja) 2004-05-18 2005-12-02 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US7242051B2 (en) * 2005-05-20 2007-07-10 Silicon Storage Technology, Inc. Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7557032B2 (en) 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7416943B2 (en) * 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7525841B2 (en) * 2006-06-14 2009-04-28 Micron Technology, Inc. Programming method for NAND flash
US7977190B2 (en) 2006-06-21 2011-07-12 Micron Technology, Inc. Memory devices having reduced interference between floating gates and methods of fabricating such devices
US7883965B2 (en) * 2006-07-31 2011-02-08 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
JP2007129254A (ja) * 2006-12-28 2007-05-24 Toshiba Corp 半導体装置及びその製造方法
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
JP2008270351A (ja) 2007-04-17 2008-11-06 Toshiba Corp 不揮発性半導体記憶装置
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101903975B1 (ko) 2008-07-16 2018-10-04 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
KR101001464B1 (ko) * 2008-08-01 2010-12-14 주식회사 하이닉스반도체 반도체 메모리 소자 및 그의 형성방법
JP5522915B2 (ja) 2008-09-30 2014-06-18 ローム株式会社 半導体記憶装置およびその製造方法
US7820510B2 (en) * 2009-03-16 2010-10-26 United Microelectronics Corp. Method of fabricating a flash memory and an isolating structure applied to a flash memory
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
JP2012019020A (ja) * 2010-07-07 2012-01-26 Toshiba Corp 不揮発性記憶装置
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8916920B2 (en) * 2011-07-19 2014-12-23 Macronix International Co., Ltd. Memory structure with planar upper surface
KR102002942B1 (ko) * 2013-04-18 2019-07-24 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 그 제조방법

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JP3238576B2 (ja) * 1994-08-19 2001-12-17 株式会社東芝 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
KR100221940B1 (ko) 1999-09-15
JP3469362B2 (ja) 2003-11-25
JPH08125148A (ja) 1996-05-17
US5949101A (en) 1999-09-07

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