DE69618928D1 - Halbleiterspeichergerät mit Zeilenredundanz - Google Patents

Halbleiterspeichergerät mit Zeilenredundanz

Info

Publication number: DE69618928D1
Authority: DE; Germany
Prior art keywords: memory device; semiconductor memory; line redundancy; redundancy; line
Prior art date: 1996-04-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE69618928T

Other languages

English (en)

Inventor

Luigi Pascucci

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

STMicroelectronics SRL

Original Assignee

STMicroelectronics SRL

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1996-04-18

Filing date

1996-04-18

Publication date

2002-03-14

1996-04-18 Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL

2002-03-14 Application granted granted Critical

2002-03-14 Publication of DE69618928D1 publication Critical patent/DE69618928D1/de

2016-04-19 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Links

239000004065 semiconductor Substances 0.000 title 1

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability

DE69618928T 1996-04-18 1996-04-18 Halbleiterspeichergerät mit Zeilenredundanz Expired - Lifetime DE69618928D1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
EP96830217A EP0802483B1 (de)	1996-04-18	1996-04-18	Halbleiterspeichergerät mit Zeilenredundanz

Publications (1)

Publication Number	Publication Date
DE69618928D1 true DE69618928D1 (de)	2002-03-14

Family

ID=8225883

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69618928T Expired - Lifetime DE69618928D1 (de)	1996-04-18	1996-04-18	Halbleiterspeichergerät mit Zeilenredundanz

Country Status (3)

Country	Link
US (1)	US5889710A (de)
EP (1)	EP0802483B1 (de)
DE (1)	DE69618928D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH10302497A (ja) *	1997-04-28	1998-11-13	Fujitsu Ltd	不良アドレスの代替方法、半導体記憶装置、及び、半導体装置
US6052746A (en) *	1998-04-14	2000-04-18	Motorola, Inc.	Integrated circuit having programmable pull device configured to enable/disable first function in favor of second function according to predetermined scheme before/after reset
US6330635B1 (en) *	1999-04-16	2001-12-11	Intel Corporation	Multiple user interfaces for an integrated flash device
US6314030B1 (en)	2000-06-14	2001-11-06	Micron Technology, Inc.	Semiconductor memory having segmented row repair
US6728123B2 (en)	2002-04-15	2004-04-27	International Business Machines Corporation	Redundant array architecture for word replacement in CAM
DE60222891T2 (de) *	2002-08-13	2008-07-24	Stmicroelectronics S.R.L., Agrate Brianza	Nichtflüchtige Speichervorrichtung und Selbstreparatur-Verfahren
US7035152B1 (en) *	2004-10-14	2006-04-25	Micron Technology, Inc.	System and method for redundancy memory decoding
US7518196B2 (en) *	2005-02-23	2009-04-14	Intel Corporation	Field effect transistor with narrow bandgap source and drain regions and method of fabrication
JP4524636B2 (ja) *	2005-03-24	2010-08-18	エルピーダメモリ株式会社	半導体記憶装置
US7858481B2 (en) *	2005-06-15	2010-12-28	Intel Corporation	Method for fabricating transistor with thinned channel
US7479421B2 (en) *	2005-09-28	2009-01-20	Intel Corporation	Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) *	2005-09-28	2007-04-26	Doyle Brian S	CMOS devices with a single work function gate electrode and method of fabrication
KR102117633B1 (ko) *	2013-09-12	2020-06-02	에스케이하이닉스 주식회사	셀프 리페어 장치

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JP2577724B2 (ja) *	1986-07-31	1997-02-05	三菱電機株式会社	半導体記憶装置
DE3685654D1 (de) *	1986-08-22	1992-07-16	Ibm	Dekodierverfahren und -schaltungsanordnung fuer einen redundanten cmos-halbleiterspeicher.
JPS6433800A (en) *	1987-07-29	1989-02-03	Toshiba Corp	Semiconductor memory
DE69411532T2 (de) *	1994-02-17	1999-03-04	St Microelectronics Srl	Verfahren zur Programmierung von Redundanzregistern in einer Zeilenredundanzschaltung für einen Halbleiterspeicherbaustein

1996
- 1996-04-18 EP EP96830217A patent/EP0802483B1/de not_active Expired - Lifetime
- 1996-04-18 DE DE69618928T patent/DE69618928D1/de not_active Expired - Lifetime
1997
- 1997-04-17 US US08/842,835 patent/US5889710A/en not_active Expired - Lifetime

Also Published As

Publication number	Publication date
EP0802483B1 (de)	2002-01-30
EP0802483A1 (de)	1997-10-22
US5889710A (en)	1999-03-30

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Legal Events

Date	Code	Title	Description
2002-09-26	8332	No legal effect for de