DE69427599D1 - Basiszelle für ein Gate-Array mit doppeltem Puffer - Google Patents

Basiszelle für ein Gate-Array mit doppeltem Puffer

Info

Publication number
DE69427599D1
DE69427599D1 DE69427599T DE69427599T DE69427599D1 DE 69427599 D1 DE69427599 D1 DE 69427599D1 DE 69427599 T DE69427599 T DE 69427599T DE 69427599 T DE69427599 T DE 69427599T DE 69427599 D1 DE69427599 D1 DE 69427599D1
Authority
DE
Germany
Prior art keywords
gate array
basic cell
double buffer
buffer
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69427599T
Other languages
English (en)
Other versions
DE69427599T2 (de
Inventor
Charles David Waggoner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69427599D1 publication Critical patent/DE69427599D1/de
Application granted granted Critical
Publication of DE69427599T2 publication Critical patent/DE69427599T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11809—Microarchitecture
    • H01L2027/11829—Isolation techniques
    • H01L2027/11831—FET isolation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69427599T 1993-01-29 1994-01-28 Basiszelle für ein Gate-Array mit doppeltem Puffer Expired - Fee Related DE69427599T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/011,390 US5420447A (en) 1993-01-29 1993-01-29 Double buffer base gate array cell

Publications (2)

Publication Number Publication Date
DE69427599D1 true DE69427599D1 (de) 2001-08-09
DE69427599T2 DE69427599T2 (de) 2002-05-23

Family

ID=21750178

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427599T Expired - Fee Related DE69427599T2 (de) 1993-01-29 1994-01-28 Basiszelle für ein Gate-Array mit doppeltem Puffer

Country Status (4)

Country Link
US (1) US5420447A (de)
EP (1) EP0609096B1 (de)
JP (1) JPH077143A (de)
DE (1) DE69427599T2 (de)

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JP3778581B2 (ja) * 1993-07-05 2006-05-24 三菱電機株式会社 半導体装置およびその製造方法
US5419457A (en) * 1993-08-30 1995-05-30 Electrocom Gard Ltd. System for sorting mail pieces on multiple levels and a method for performing the same
JP3520659B2 (ja) * 1995-03-30 2004-04-19 セイコーエプソン株式会社 複数の電源電圧で駆動されるゲートアレイ及びそれを用いた電子機器
US5764533A (en) * 1995-08-01 1998-06-09 Sun Microsystems, Inc. Apparatus and methods for generating cell layouts
US5990502A (en) * 1995-12-29 1999-11-23 Lsi Logic Corporation High density gate array cell architecture with metallization routing tracks having a variable pitch
US5818730A (en) * 1996-12-05 1998-10-06 Xilinx, Inc. FPGA one turn routing structure and method using minimum diffusion area
US5780883A (en) * 1997-02-28 1998-07-14 Translogic Technology, Inc. Gate array architecture for multiplexer based circuits
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
KR100233285B1 (ko) * 1997-05-23 1999-12-01 김영환 Cmos 로직 게이트 어레이
US6445049B1 (en) * 1997-06-30 2002-09-03 Artisan Components, Inc. Cell based array comprising logic, transfer and drive cells
US5982199A (en) * 1998-01-13 1999-11-09 Advanced Micro Devices, Inc. Faster NAND for microprocessors utilizing unevenly sub-nominal P-channel and N-channel CMOS transistors with reduced overlap capacitance
JP3152642B2 (ja) * 1998-01-29 2001-04-03 三洋電機株式会社 半導体集積回路装置
US6242814B1 (en) * 1998-07-31 2001-06-05 Lsi Logic Corporation Universal I/O pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly
US6480032B1 (en) * 1999-03-04 2002-11-12 Intel Corporation Gate array architecture
JP3231741B2 (ja) * 1999-06-28 2001-11-26 エヌイーシーマイクロシステム株式会社 スタンダードセル、スタンダードセル列、スタンダードセルの配置配線装置および配置配線方法
JP3647323B2 (ja) * 1999-07-30 2005-05-11 富士通株式会社 半導体集積回路
JP2001194574A (ja) 2000-01-11 2001-07-19 Fuji Photo Film Co Ltd 移動機構、レンズ鏡胴、及び撮像装置
JP2001237280A (ja) 2000-02-22 2001-08-31 Nec Corp テープキャリア型半導体装置および可撓性フィルム接続基板
JP2002026296A (ja) * 2000-06-22 2002-01-25 Internatl Business Mach Corp <Ibm> 半導体集積回路装置
JP4175649B2 (ja) * 2004-07-22 2008-11-05 松下電器産業株式会社 半導体装置
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
JP5064321B2 (ja) * 2008-07-09 2012-10-31 パナソニック株式会社 半導体装置
JP5599395B2 (ja) 2008-07-16 2014-10-01 テラ イノヴェイションズ インコーポレイテッド 動的アレイアーキテクチャにおけるセル位相整合及び配置の方法及びその実施
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8390331B2 (en) * 2009-12-29 2013-03-05 Nxp B.V. Flexible CMOS library architecture for leakage power and variability reduction
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
FR2968128B1 (fr) 2010-11-26 2013-01-04 St Microelectronics Sa Cellule precaracterisee pour circuit intégré
WO2012144295A1 (ja) * 2011-04-20 2012-10-26 ルネサスエレクトロニクス株式会社 半導体装置
US9691750B2 (en) * 2015-01-30 2017-06-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and layout method thereof
KR102308779B1 (ko) 2017-04-10 2021-10-05 삼성전자주식회사 이종 컨택들을 구비하는 집적 회로 및 이를 포함하는 반도체 장치
CN110047813B (zh) * 2018-01-15 2021-04-06 联华电子股份有限公司 半导体元件
US10896912B2 (en) * 2019-03-20 2021-01-19 International Business Machines Corporation Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5890758A (ja) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp 相補形集積回路装置
JPS6080251A (ja) * 1983-10-08 1985-05-08 Fujitsu Ltd ゲ−トアレイ大規模集積回路装置
JPS6164337A (ja) * 1984-09-06 1986-04-02 Toyota Motor Corp モノリス触媒の製造方法
DE8526950U1 (de) * 1985-09-20 1986-12-04 Siemens AG, 1000 Berlin und 8000 München Gate-Array mit einlagiger Metallverdrahtung
US4884115A (en) * 1987-02-27 1989-11-28 Siemens Aktiengesellschaft Basic cell for a gate array arrangement in CMOS Technology
US5187556A (en) * 1990-08-13 1993-02-16 Kawasaki Steel Corporation Cmos master slice

Also Published As

Publication number Publication date
EP0609096B1 (de) 2001-07-04
EP0609096A1 (de) 1994-08-03
US5420447A (en) 1995-05-30
JPH077143A (ja) 1995-01-10
DE69427599T2 (de) 2002-05-23

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Legal Events

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8339 Ceased/non-payment of the annual fee