DE3586385D1 - Integrierte gate-matrixstruktur. - Google Patents

Integrierte gate-matrixstruktur.

Info

Publication number
DE3586385D1
DE3586385D1 DE8585307023T DE3586385T DE3586385D1 DE 3586385 D1 DE3586385 D1 DE 3586385D1 DE 8585307023 T DE8585307023 T DE 8585307023T DE 3586385 T DE3586385 T DE 3586385T DE 3586385 D1 DE3586385 D1 DE 3586385D1
Authority
DE
Germany
Prior art keywords
matrix structure
integrated gate
gate matrix
integrated
matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585307023T
Other languages
English (en)
Other versions
DE3586385T2 (de
Inventor
Yoshihisa Takayama
Kazuyuki Kawauchi
Shigeru Fujii
Toshihiko Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59206144A external-priority patent/JPH0828481B2/ja
Priority claimed from JP59220447A external-priority patent/JPH0828482B2/ja
Priority claimed from JP59220450A external-priority patent/JPH07105479B2/ja
Priority claimed from JP59274504A external-priority patent/JPS61156751A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3586385D1 publication Critical patent/DE3586385D1/de
Application granted granted Critical
Publication of DE3586385T2 publication Critical patent/DE3586385T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8585307023T 1984-10-03 1985-10-01 Integrierte gate-matrixstruktur. Expired - Fee Related DE3586385T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP59206144A JPH0828481B2 (ja) 1984-10-03 1984-10-03 ゲ−トアレイマスタスライス集積回路装置
JP59220447A JPH0828482B2 (ja) 1984-10-22 1984-10-22 ゲ−トアレイマスタスライス集積回路装置におけるクリツプ方法
JP59220450A JPH07105479B2 (ja) 1984-10-22 1984-10-22 ゲ−トアレイマスタスライス集積回路装置におけるクリツプ方法
JP59274504A JPS61156751A (ja) 1984-12-28 1984-12-28 半導体集積回路

Publications (2)

Publication Number Publication Date
DE3586385D1 true DE3586385D1 (de) 1992-08-27
DE3586385T2 DE3586385T2 (de) 1993-01-07

Family

ID=27476294

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585307023T Expired - Fee Related DE3586385T2 (de) 1984-10-03 1985-10-01 Integrierte gate-matrixstruktur.

Country Status (4)

Country Link
US (1) US4661815A (de)
EP (1) EP0177336B1 (de)
KR (1) KR900005150B1 (de)
DE (1) DE3586385T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62119936A (ja) * 1985-11-19 1987-06-01 Fujitsu Ltd コンプリメンタリ−ｌｓｉチツプ
US4884118A (en) * 1986-05-19 1989-11-28 Lsi Logic Corporation Double metal HCMOS compacted array
JPS62276852A (ja) * 1986-05-23 1987-12-01 Mitsubishi Electric Corp 半導体集積回路装置
EP0248266A3 (de) * 1986-06-06 1990-04-25 Siemens Aktiengesellschaft Logikschaltung mit einer Mehrzahl von zueinander komplementären Feldeffekttransistoren
JPH0789568B2 (ja) * 1986-06-19 1995-09-27 日本電気株式会社 集積回路装置
JPH0738414B2 (ja) * 1987-01-09 1995-04-26 株式会社東芝 半導体集積回路
US4819047A (en) * 1987-05-15 1989-04-04 Advanced Micro Devices, Inc. Protection system for CMOS integrated circuits
JP2606845B2 (ja) * 1987-06-19 1997-05-07 富士通株式会社 半導体集積回路
JPH0254576A (ja) * 1988-08-18 1990-02-23 Mitsubishi Electric Corp ゲートアレイ
JPH0727968B2 (ja) * 1988-12-20 1995-03-29 株式会社東芝 半導体集積回路装置
US4928160A (en) * 1989-01-17 1990-05-22 Ncr Corporation Gate isolated base cell structure with off-grid gate polysilicon pattern
US5298774A (en) * 1990-01-11 1994-03-29 Mitsubishi Denki Kabushiki Kaisha Gate array system semiconductor integrated circuit device
JPH04103161A (ja) * 1990-08-22 1992-04-06 Toshiba Corp バイポーラトランジスタ・絶縁ゲート型トランジスタ混載半導体装置
US5063429A (en) * 1990-09-17 1991-11-05 Ncr Corporation High density input/output cell arrangement for integrated circuits
JP3084740B2 (ja) * 1990-10-30 2000-09-04 日本電気株式会社 半導体集積回路
US5155390A (en) * 1991-07-25 1992-10-13 Motorola, Inc. Programmable block architected heterogeneous integrated circuit
US5343058A (en) * 1991-11-18 1994-08-30 Vlsi Technology, Inc. Gate array bases with flexible routing
US5308798A (en) * 1992-11-12 1994-05-03 Vlsi Technology, Inc. Preplacement method for weighted net placement integrated circuit design layout tools
US5757208A (en) * 1996-05-01 1998-05-26 Motorola, Inc. Programmable array and method for routing power busses therein
JP3553334B2 (ja) * 1997-10-06 2004-08-11 株式会社ルネサステクノロジ 半導体装置
JP3526450B2 (ja) * 2001-10-29 2004-05-17 株式会社東芝 半導体集積回路およびスタンダードセル配置設計方法
WO2011077664A1 (ja) 2009-12-25 2011-06-30 パナソニック株式会社 半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4161662A (en) * 1976-01-22 1979-07-17 Motorola, Inc. Standardized digital logic chip
JPH077825B2 (ja) * 1981-08-13 1995-01-30 富士通株式会社 ゲートアレイの製造方法
DE3474485D1 (en) * 1983-03-09 1988-11-10 Toshiba Kk Semiconductor integrated circuit with gate-array arrangement
JPS59163837A (ja) * 1983-03-09 1984-09-14 Toshiba Corp 半導体集積回路
JPS6017932A (ja) * 1983-07-09 1985-01-29 Fujitsu Ltd ゲ−ト・アレイ
US4602270A (en) * 1985-05-17 1986-07-22 United Technologies Corporation Gate array with reduced isolation

Also Published As

Publication number Publication date
EP0177336B1 (de) 1992-07-22
US4661815A (en) 1987-04-28
KR900005150B1 (en) 1990-07-20
EP0177336A2 (de) 1986-04-09
KR860003662A (ko) 1986-05-28
EP0177336A3 (en) 1987-04-15
DE3586385T2 (de) 1993-01-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee