DE69008702D1 - Halbleiterpackung mit von Trägern trennbaren Leitern. - Google Patents

Halbleiterpackung mit von Trägern trennbaren Leitern.

Info

Publication number
DE69008702D1
DE69008702D1 DE69008702T DE69008702T DE69008702D1 DE 69008702 D1 DE69008702 D1 DE 69008702D1 DE 69008702 T DE69008702 T DE 69008702T DE 69008702 T DE69008702 T DE 69008702T DE 69008702 D1 DE69008702 D1 DE 69008702D1
Authority
DE
Germany
Prior art keywords
conductors
carriers
separated
semiconductor package
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69008702T
Other languages
English (en)
Other versions
DE69008702T2 (de
Inventor
George W Hawkins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69008702D1 publication Critical patent/DE69008702D1/de
Publication of DE69008702T2 publication Critical patent/DE69008702T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE69008702T 1990-01-29 1990-12-24 Halbleiterpackung mit von Trägern trennbaren Leitern. Expired - Fee Related DE69008702T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/471,470 US4989069A (en) 1990-01-29 1990-01-29 Semiconductor package having leads that break-away from supports

Publications (2)

Publication Number Publication Date
DE69008702D1 true DE69008702D1 (de) 1994-06-09
DE69008702T2 DE69008702T2 (de) 1994-11-24

Family

ID=23871757

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69008702T Expired - Fee Related DE69008702T2 (de) 1990-01-29 1990-12-24 Halbleiterpackung mit von Trägern trennbaren Leitern.

Country Status (5)

Country Link
US (1) US4989069A (de)
EP (1) EP0439825B1 (de)
JP (1) JP2570917B2 (de)
KR (1) KR100222157B1 (de)
DE (1) DE69008702T2 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) * 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US5583375A (en) * 1990-06-11 1996-12-10 Hitachi, Ltd. Semiconductor device with lead structure within the planar area of the device
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US7198969B1 (en) * 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US20010030370A1 (en) * 1990-09-24 2001-10-18 Khandros Igor Y. Microelectronic assembly having encapsulated wire bonding leads
US5258330A (en) * 1990-09-24 1993-11-02 Tessera, Inc. Semiconductor chip assemblies with fan-in leads
US5148266A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5679977A (en) * 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5168368A (en) * 1991-05-09 1992-12-01 International Business Machines Corporation Lead frame-chip package with improved configuration
DE4217598A1 (de) * 1992-05-27 1993-12-02 Siemens Nixdorf Inf Syst Einbausystem für auf Leiterplatten montierte hochintegrierte, gehäuselose Bausteine
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
US5977618A (en) * 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US5915752A (en) * 1992-07-24 1999-06-29 Tessera, Inc. Method of making connections to a semiconductor chip assembly
US5420758A (en) * 1992-09-10 1995-05-30 Vlsi Technology, Inc. Integrated circuit package using a multi-layer PCB in a plastic package
US5414298A (en) * 1993-03-26 1995-05-09 Tessera, Inc. Semiconductor chip assemblies and components with pressure contact
US20030199179A1 (en) * 1993-11-16 2003-10-23 Formfactor, Inc. Contact tip structure for microelectronic interconnection elements and method of making same
US5820014A (en) 1993-11-16 1998-10-13 Form Factor, Inc. Solder preforms
US20020053734A1 (en) * 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
US7073254B2 (en) * 1993-11-16 2006-07-11 Formfactor, Inc. Method for mounting a plurality of spring contact elements
AU4160096A (en) * 1994-11-15 1996-06-06 Formfactor, Inc. Probe card assembly and kit, and methods of using same
US6826827B1 (en) * 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
US20020151111A1 (en) * 1995-05-08 2002-10-17 Tessera, Inc. P-connection components with frangible leads and bus
KR100407055B1 (ko) 1995-09-18 2004-03-31 테세라, 인코포레이티드 유전체층을갖는마이크로전자리드구조
US8033838B2 (en) * 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
US6880245B2 (en) * 1996-03-12 2005-04-19 International Business Machines Corporation Method for fabricating a structure for making contact with an IC device
US5937276A (en) 1996-12-13 1999-08-10 Tessera, Inc. Bonding lead structure with enhanced encapsulation
US6724203B1 (en) 1997-10-30 2004-04-20 International Business Machines Corporation Full wafer test configuration using memory metals
US6980017B1 (en) * 1999-03-10 2005-12-27 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6627478B2 (en) * 1999-05-24 2003-09-30 Tessera, Inc. Method of making a microelectronic assembly with multiple lead deformation using differential thermal expansion/contraction
US6657286B2 (en) * 2000-09-21 2003-12-02 Tessera, Inc. Microelectronic assembly formation with lead displacement
US6376266B1 (en) * 2000-11-06 2002-04-23 Semiconductor Components Industries Llc Semiconductor package and method for forming same
US20030038356A1 (en) * 2001-08-24 2003-02-27 Derderian James M Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods
US20040105244A1 (en) * 2002-08-06 2004-06-03 Ilyas Mohammed Lead assemblies with offset portions and microelectronic assemblies with leads having offset portions
US20040222518A1 (en) * 2003-02-25 2004-11-11 Tessera, Inc. Ball grid array with bumps
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
TWI267151B (en) * 2004-10-14 2006-11-21 Advanced Semiconductor Eng Processing method during a package process
US20080150101A1 (en) * 2006-12-20 2008-06-26 Tessera, Inc. Microelectronic packages having improved input/output connections and methods therefor
US20090140433A1 (en) * 2007-11-30 2009-06-04 Alces Technology, Inc. MEMS chip-to-chip interconnects
JP5574667B2 (ja) * 2009-10-21 2014-08-20 キヤノン株式会社 パッケージ、半導体装置、それらの製造方法及び機器
US9137903B2 (en) 2010-12-21 2015-09-15 Tessera, Inc. Semiconductor chip assembly and method for making same
JP2017069333A (ja) * 2015-09-29 2017-04-06 ファナック株式会社 プリント基板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3842189A (en) * 1973-01-08 1974-10-15 Rca Corp Contact array and method of making the same
US4465898A (en) * 1981-07-27 1984-08-14 Texas Instruments Incorporated Carrier for integrated circuit
JPS58169948A (ja) * 1982-03-30 1983-10-06 Fujitsu Ltd 樹脂封止型半導体装置
US4672421A (en) * 1984-04-02 1987-06-09 Motorola, Inc. Semiconductor packaging and method
JPH0325410Y2 (de) * 1985-08-10 1991-06-03
JPS6298759A (ja) * 1985-10-25 1987-05-08 Mitsubishi Electric Corp 電子デバイス
US4872047A (en) * 1986-11-07 1989-10-03 Olin Corporation Semiconductor die attach system

Also Published As

Publication number Publication date
EP0439825B1 (de) 1994-05-04
JP2570917B2 (ja) 1997-01-16
DE69008702T2 (de) 1994-11-24
KR910015035A (ko) 1991-08-31
US4989069A (en) 1991-01-29
JPH0750359A (ja) 1995-02-21
EP0439825A2 (de) 1991-08-07
KR100222157B1 (ko) 1999-10-01
EP0439825A3 (en) 1991-09-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee