DE3889570D1 - Halbleiterschaltung. - Google Patents

Halbleiterschaltung.

Info

Publication number
DE3889570D1
DE3889570D1 DE3889570T DE3889570T DE3889570D1 DE 3889570 D1 DE3889570 D1 DE 3889570D1 DE 3889570 T DE3889570 T DE 3889570T DE 3889570 T DE3889570 T DE 3889570T DE 3889570 D1 DE3889570 D1 DE 3889570D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
semiconductor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3889570T
Other languages
English (en)
Other versions
DE3889570T2 (de
Inventor
Kimimasa Imai
Hiroshi Shinya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3889570D1 publication Critical patent/DE3889570D1/de
Publication of DE3889570T2 publication Critical patent/DE3889570T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/2893—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
DE3889570T 1987-03-26 1988-03-16 Halbleiterschaltung. Expired - Fee Related DE3889570T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62072103A JP2549109B2 (ja) 1987-03-26 1987-03-26 半導体回路

Publications (2)

Publication Number Publication Date
DE3889570D1 true DE3889570D1 (de) 1994-06-23
DE3889570T2 DE3889570T2 (de) 1994-09-29

Family

ID=13479731

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889570T Expired - Fee Related DE3889570T2 (de) 1987-03-26 1988-03-16 Halbleiterschaltung.

Country Status (5)

Country Link
US (1) US4849653A (de)
EP (1) EP0283915B1 (de)
JP (1) JP2549109B2 (de)
KR (1) KR910005372B1 (de)
DE (1) DE3889570T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914318A (en) * 1988-12-30 1990-04-03 Intel Corporation Latch circuit for a programmable logic device using dual n-type transistors
US4958088A (en) * 1989-06-19 1990-09-18 Micron Technology, Inc. Low power three-stage CMOS input buffer with controlled switching
JP2621993B2 (ja) * 1989-09-05 1997-06-18 株式会社東芝 フリップフロップ回路
US5034623A (en) * 1989-12-28 1991-07-23 Texas Instruments Incorporated Low power, TTL level CMOS input buffer with hysteresis
US5365122A (en) * 1990-11-09 1994-11-15 Vlsi Technology, Inc. Meta stable resistant signal detector
JP3225528B2 (ja) * 1991-03-26 2001-11-05 日本電気株式会社 レジスタ回路
US5280203A (en) * 1992-05-15 1994-01-18 Altera Corporation Look-ahead asynchronous register set/reset in programmable logic device
US5365125A (en) * 1992-07-23 1994-11-15 Xilinx, Inc. Logic cell for field programmable gate array having optional internal feedback and optional cascade
US5319254A (en) * 1992-07-23 1994-06-07 Xilinx, Inc. Logic cell which can be configured as a latch without static one's problem
US5646547A (en) * 1994-04-28 1997-07-08 Xilinx, Inc. Logic cell which can be configured as a latch without static one's problem
US5287394A (en) * 1993-03-22 1994-02-15 Advanced Micro Devices, Inc. Fast counter with uniform delay structures
US5489866A (en) * 1994-04-19 1996-02-06 Xilinx, Inc. High speed and low noise margin schmitt trigger with controllable trip point
US6369630B1 (en) * 1999-11-24 2002-04-09 Bae Systems Information And Electronic Systems Integration Inc. Single-event upset hardened reconfigurable bi-stable CMOS latch
JP2005151170A (ja) * 2003-11-14 2005-06-09 Renesas Technology Corp 半導体集積回路
JP5440038B2 (ja) * 2009-09-02 2014-03-12 日本電気株式会社 電源インタフェース、受信回路、集積回路、及び信号伝送方法
US8508276B2 (en) * 2010-08-25 2013-08-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including latch circuit
WO2012029871A1 (ja) * 2010-09-02 2012-03-08 シャープ株式会社 信号処理回路、ドライバ回路、表示装置
KR102487109B1 (ko) * 2015-12-15 2023-01-09 엘지디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4735751U (de) * 1971-05-07 1972-12-20
JPS4995550A (de) * 1973-01-12 1974-09-10
JPS5779726A (en) * 1980-11-04 1982-05-19 Nec Corp Highly reliable logical circuit
US4687954A (en) * 1984-03-06 1987-08-18 Kabushiki Kaisha Toshiba CMOS hysteresis circuit with enable switch or natural transistor
JPS61128621A (ja) * 1984-11-27 1986-06-16 Rohm Co Ltd フリツプフロツプ回路
JPS61283092A (ja) * 1985-06-06 1986-12-13 Mitsubishi Electric Corp リセツトあるいはセツト付記憶回路を有した半導体集積回路

Also Published As

Publication number Publication date
JPS63237608A (ja) 1988-10-04
KR910005372B1 (ko) 1991-07-29
DE3889570T2 (de) 1994-09-29
JP2549109B2 (ja) 1996-10-30
EP0283915A2 (de) 1988-09-28
EP0283915B1 (de) 1994-05-18
US4849653A (en) 1989-07-18
KR880012004A (ko) 1988-10-31
EP0283915A3 (en) 1990-07-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee