DE68907496D1 - Dekodierer-pufferschaltung, die in einer halbleiterspeichereinrichtung enthalten ist. - Google Patents

Dekodierer-pufferschaltung, die in einer halbleiterspeichereinrichtung enthalten ist.

Info

Publication number: DE68907496D1
Authority: DE; Germany
Prior art keywords: memory device; semiconductor memory; buffer circuit; decoder buffer; circuit contained
Prior art date: 1988-02-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE8989102806T

Other languages

English (en)

Other versions

DE68907496T2 (de

Inventor

Masahiko Kashimura

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Electronics Corp

Original Assignee

NEC Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1988-02-19

Filing date

1989-02-17

Publication date

1993-08-19

1989-02-17 Application filed by NEC Corp filed Critical NEC Corp

1993-08-19 Application granted granted Critical

1993-08-19 Publication of DE68907496D1 publication Critical patent/DE68907496D1/de

1993-10-21 Publication of DE68907496T2 publication Critical patent/DE68907496T2/de

2009-02-18 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

239000004065 semiconductor Substances 0.000 title 1

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Static Random-Access Memory (AREA)
Read Only Memory (AREA)
Dram (AREA)

DE89102806T 1988-02-19 1989-02-17 Dekodierer-Pufferschaltung, die in einer Halbleiterspeichereinrichtung enthalten ist. Expired - Fee Related DE68907496T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP3685088A JPH0766669B2 (ja)	1988-02-19	1988-02-19	デコーダバッファ回路

Publications (2)

Publication Number	Publication Date
DE68907496D1 true DE68907496D1 (de)	1993-08-19
DE68907496T2 DE68907496T2 (de)	1993-10-21

Family

ID=12481244

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE89102806T Expired - Fee Related DE68907496T2 (de)	1988-02-19	1989-02-17	Dekodierer-Pufferschaltung, die in einer Halbleiterspeichereinrichtung enthalten ist.

Country Status (4)

Country	Link
US (1)	US4953133A (de)
EP (1)	EP0329182B1 (de)
JP (1)	JPH0766669B2 (de)
DE (1)	DE68907496T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
KR100254134B1 (ko) *	1991-11-08	2000-04-15	나시모토 류우조오	대기시 전류저감회로를 가진 반도체 집적회로
KR0113252Y1 (ko) *	1991-12-24	1998-04-14	문정환	워드라인 전압 공급회로
US5274278A (en) *	1991-12-31	1993-12-28	Intel Corporation	High-speed tri-level decoder with dual-voltage isolation
US5282176A (en) *	1992-09-30	1994-01-25	Intel Corporation	High speed input receiver and wordline driver circuit
KR0121134B1 (ko) *	1994-09-14	1997-11-10	문정환	반도체 메모리장치의 워드라인드라이버
US5724302A (en) *	1995-07-10	1998-03-03	Intel Corporation	High density decoder
AU1960297A (en) *	1997-02-12	1998-09-08	Intel Corporation	High density decoder
CN107799089B (zh) *	2017-12-13	2021-02-09	京东方科技集团股份有限公司	像素电路和显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4085460A (en) *	1976-04-05	1978-04-18	Sperry Rand Corporation	Decoder buffer circuit for MNOS memory
JPS56101687A (en) *	1979-12-27	1981-08-14	Fujitsu Ltd	Semiconductor memory circuit
JPS583185A (ja) *	1981-06-30	1983-01-08	Fujitsu Ltd	デコ−ダ回路
US4385369A (en) *	1981-08-21	1983-05-24	Mostek Corporation	Semiconductor memory address buffer having power down mode
JPS5873097A (ja) *	1981-10-27	1983-05-02	Nec Corp	デコ−ダ−回路
JPS58185091A (ja) *	1982-04-24	1983-10-28	Toshiba Corp	昇圧電圧出力回路および昇圧電圧出力回路を備えたアドレスデコ−ド回路
JPS60115094A (ja) *	1983-11-16	1985-06-21	Fujitsu Ltd	ダイナミツクランダムアクセスメモリ装置
JPS60224187A (ja) *	1984-04-20	1985-11-08	Seiko Epson Corp	アドレス選択回路
JPS61133093A (ja) *	1984-12-03	1986-06-20	Oki Electric Ind Co Ltd	半導体メモリ装置
FR2591789B1 (fr) *	1985-12-17	1988-02-19	Labo Electronique Physique	Circuit decodeur pour memoire ram statique

1988
- 1988-02-19 JP JP3685088A patent/JPH0766669B2/ja not_active Expired - Fee Related
1989
- 1989-02-17 DE DE89102806T patent/DE68907496T2/de not_active Expired - Fee Related
- 1989-02-17 EP EP89102806A patent/EP0329182B1/de not_active Expired - Lifetime
- 1989-02-21 US US07/313,202 patent/US4953133A/en not_active Expired - Lifetime

Also Published As

Publication number	Publication date
DE68907496T2 (de)	1993-10-21
EP0329182A2 (de)	1989-08-23
EP0329182A3 (de)	1991-03-13
US4953133A (en)	1990-08-28
JPH0766669B2 (ja)	1995-07-19
JPH01211396A (ja)	1989-08-24
EP0329182B1 (de)	1993-07-14

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Legal Events

Date	Code	Title	Description
1994-08-11	8364	No opposition during term of opposition
2003-06-12	8327	Change in the person/name/address of the patent owner	Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP
2007-12-13	8339	Ceased/non-payment of the annual fee